mirror of https://github.com/xemu-project/xemu.git
libqos: Add 64-bit PCI IO accessors
Currently the libqos PCI layer includes accessor helpers for 8, 16 and 32 bit reads and writes. It's likely that we'll want 64-bit accesses in the future (plenty of modern peripherals will have 64-bit reigsters). This adds them. For PIO (not MMIO) accesses on the PC backend, this is implemented as two 32-bit ins or outs. That's not ideal but AFAICT x86 doesn't have 64-bit versions of in and out. This patch also converts the single current user of 64-bit accesses - virtio-pci.c to use the new mechanism, rather than a sequence of 8 byte reads. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org>
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@ -57,6 +57,17 @@ static void qpci_pc_pio_writel(QPCIBus *bus, uint32_t addr, uint32_t val)
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outl(addr, val);
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}
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static uint64_t qpci_pc_pio_readq(QPCIBus *bus, uint32_t addr)
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{
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return (uint64_t)inl(addr) + ((uint64_t)inl(addr + 4) << 32);
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}
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static void qpci_pc_pio_writeq(QPCIBus *bus, uint32_t addr, uint64_t val)
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{
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outl(addr, val & 0xffffffff);
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outl(addr + 4, val >> 32);
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}
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static void qpci_pc_memread(QPCIBus *bus, uint32_t addr, void *buf, size_t len)
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{
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memread(addr, buf, len);
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@ -113,10 +124,12 @@ QPCIBus *qpci_init_pc(QGuestAllocator *alloc)
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ret->bus.pio_readb = qpci_pc_pio_readb;
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ret->bus.pio_readw = qpci_pc_pio_readw;
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ret->bus.pio_readl = qpci_pc_pio_readl;
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ret->bus.pio_readq = qpci_pc_pio_readq;
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ret->bus.pio_writeb = qpci_pc_pio_writeb;
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ret->bus.pio_writew = qpci_pc_pio_writew;
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ret->bus.pio_writel = qpci_pc_pio_writel;
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ret->bus.pio_writeq = qpci_pc_pio_writeq;
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ret->bus.memread = qpci_pc_memread;
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ret->bus.memwrite = qpci_pc_memwrite;
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@ -78,6 +78,18 @@ static void qpci_spapr_pio_writel(QPCIBus *bus, uint32_t addr, uint32_t val)
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writel(s->pio_cpu_base + addr, bswap32(val));
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}
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static uint64_t qpci_spapr_pio_readq(QPCIBus *bus, uint32_t addr)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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return bswap64(readq(s->pio_cpu_base + addr));
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}
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static void qpci_spapr_pio_writeq(QPCIBus *bus, uint32_t addr, uint64_t val)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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writeq(s->pio_cpu_base + addr, bswap64(val));
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}
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static void qpci_spapr_memread(QPCIBus *bus, uint32_t addr,
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void *buf, size_t len)
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{
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@ -153,10 +165,12 @@ QPCIBus *qpci_init_spapr(QGuestAllocator *alloc)
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ret->bus.pio_readb = qpci_spapr_pio_readb;
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ret->bus.pio_readw = qpci_spapr_pio_readw;
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ret->bus.pio_readl = qpci_spapr_pio_readl;
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ret->bus.pio_readq = qpci_spapr_pio_readq;
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ret->bus.pio_writeb = qpci_spapr_pio_writeb;
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ret->bus.pio_writew = qpci_spapr_pio_writew;
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ret->bus.pio_writel = qpci_spapr_pio_writel;
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ret->bus.pio_writeq = qpci_spapr_pio_writeq;
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ret->bus.memread = qpci_spapr_memread;
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ret->bus.memwrite = qpci_spapr_memwrite;
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@ -262,6 +262,19 @@ uint32_t qpci_io_readl(QPCIDevice *dev, void *data)
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}
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}
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uint64_t qpci_io_readq(QPCIDevice *dev, void *data)
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{
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uintptr_t addr = (uintptr_t)data;
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if (addr < QPCI_PIO_LIMIT) {
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return dev->bus->pio_readq(dev->bus, addr);
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} else {
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uint64_t val;
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dev->bus->memread(dev->bus, addr, &val, sizeof(val));
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return le64_to_cpu(val);
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}
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}
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void qpci_io_writeb(QPCIDevice *dev, void *data, uint8_t value)
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{
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uintptr_t addr = (uintptr_t)data;
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@ -297,6 +310,18 @@ void qpci_io_writel(QPCIDevice *dev, void *data, uint32_t value)
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}
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}
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void qpci_io_writeq(QPCIDevice *dev, void *data, uint64_t value)
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{
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uintptr_t addr = (uintptr_t)data;
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if (addr < QPCI_PIO_LIMIT) {
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dev->bus->pio_writeq(dev->bus, addr, value);
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} else {
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value = cpu_to_le64(value);
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dev->bus->memwrite(dev->bus, addr, &value, sizeof(value));
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}
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}
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void qpci_memread(QPCIDevice *dev, void *data, void *buf, size_t len)
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{
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uintptr_t addr = (uintptr_t)data;
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@ -26,10 +26,12 @@ struct QPCIBus {
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uint8_t (*pio_readb)(QPCIBus *bus, uint32_t addr);
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uint16_t (*pio_readw)(QPCIBus *bus, uint32_t addr);
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uint32_t (*pio_readl)(QPCIBus *bus, uint32_t addr);
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uint64_t (*pio_readq)(QPCIBus *bus, uint32_t addr);
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void (*pio_writeb)(QPCIBus *bus, uint32_t addr, uint8_t value);
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void (*pio_writew)(QPCIBus *bus, uint32_t addr, uint16_t value);
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void (*pio_writel)(QPCIBus *bus, uint32_t addr, uint32_t value);
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void (*pio_writeq)(QPCIBus *bus, uint32_t addr, uint64_t value);
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void (*memread)(QPCIBus *bus, uint32_t addr, void *buf, size_t len);
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void (*memwrite)(QPCIBus *bus, uint32_t addr, const void *buf, size_t len);
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@ -82,10 +84,12 @@ void qpci_config_writel(QPCIDevice *dev, uint8_t offset, uint32_t value);
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uint8_t qpci_io_readb(QPCIDevice *dev, void *data);
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uint16_t qpci_io_readw(QPCIDevice *dev, void *data);
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uint32_t qpci_io_readl(QPCIDevice *dev, void *data);
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uint64_t qpci_io_readq(QPCIDevice *dev, void *data);
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void qpci_io_writeb(QPCIDevice *dev, void *data, uint8_t value);
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void qpci_io_writew(QPCIDevice *dev, void *data, uint16_t value);
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void qpci_io_writel(QPCIDevice *dev, void *data, uint32_t value);
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void qpci_io_writeq(QPCIDevice *dev, void *data, uint64_t value);
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void qpci_memread(QPCIDevice *bus, void *data, void *buf, size_t len);
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void qpci_memwrite(QPCIDevice *bus, void *data, const void *buf, size_t len);
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@ -106,22 +106,14 @@ static uint32_t qvirtio_pci_config_readl(QVirtioDevice *d, uint64_t off)
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static uint64_t qvirtio_pci_config_readq(QVirtioDevice *d, uint64_t off)
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{
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QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
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int i;
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uint64_t u64 = 0;
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uint64_t val;
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val = qpci_io_readq(dev->pdev, CONFIG_BASE(dev) + off);
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if (qvirtio_is_big_endian(d)) {
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for (i = 0; i < 8; ++i) {
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u64 |= (uint64_t)qpci_io_readb(dev->pdev, CONFIG_BASE(dev)
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+ off + i) << (7 - i) * 8;
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}
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} else {
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for (i = 0; i < 8; ++i) {
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u64 |= (uint64_t)qpci_io_readb(dev->pdev, CONFIG_BASE(dev)
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+ off + i) << i * 8;
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}
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val = bswap64(val);
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}
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return u64;
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return val;
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}
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static uint32_t qvirtio_pci_get_features(QVirtioDevice *d)
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