mirror of https://github.com/xemu-project/xemu.git
target/arm: Implement SVE scatter stores
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
5047c204d0
commit
f6dbf62a7e
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@ -958,3 +958,44 @@ DEF_HELPER_FLAGS_4(sve_st1hs_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
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DEF_HELPER_FLAGS_4(sve_st1hd_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
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DEF_HELPER_FLAGS_4(sve_st1sd_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_stbs_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_sths_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_stss_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_stbs_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_sths_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_stss_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_stbd_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_sthd_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_stsd_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_stdd_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_stbd_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_sthd_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_stsd_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_stdd_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_stbd_zd, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_sthd_zd, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_stsd_zd, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_stdd_zd, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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@ -80,6 +80,7 @@
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&rpri_load rd pg rn imm dtype nreg
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&rprr_store rd pg rn rm msz esz nreg
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&rpri_store rd pg rn imm msz esz nreg
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&rprr_scatter_store rd pg rn rm esz msz xs scale
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###########################################################################
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# Named instruction formats. These are generally used to
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@ -198,6 +199,8 @@
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@rpri_store_msz ....... msz:2 .. . imm:s4 ... pg:3 rn:5 rd:5 &rpri_store
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@rprr_store_esz_n0 ....... .. esz:2 rm:5 ... pg:3 rn:5 rd:5 \
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&rprr_store nreg=0
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@rprr_scatter_store ....... msz:2 .. rm:5 ... pg:3 rn:5 rd:5 \
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&rprr_scatter_store
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###########################################################################
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# Instruction patterns. Grouped according to the SVE encodingindex.xhtml.
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@ -825,3 +828,39 @@ ST_zpri 1110010 .. nreg:2 1.... 111 ... ..... ..... \
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# SVE store multiple structures (scalar plus scalar) (nreg != 0)
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ST_zprr 1110010 msz:2 nreg:2 ..... 011 ... ..... ..... \
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@rprr_store esz=%size_23
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# SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)
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# Require msz > 0 && msz <= esz.
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ST1_zprz 1110010 .. 11 ..... 100 ... ..... ..... \
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@rprr_scatter_store xs=0 esz=2 scale=1
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ST1_zprz 1110010 .. 11 ..... 110 ... ..... ..... \
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@rprr_scatter_store xs=1 esz=2 scale=1
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# SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets)
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# Require msz <= esz.
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ST1_zprz 1110010 .. 10 ..... 100 ... ..... ..... \
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@rprr_scatter_store xs=0 esz=2 scale=0
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ST1_zprz 1110010 .. 10 ..... 110 ... ..... ..... \
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@rprr_scatter_store xs=1 esz=2 scale=0
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# SVE 64-bit scatter store (scalar plus 64-bit scaled offset)
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# Require msz > 0
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ST1_zprz 1110010 .. 01 ..... 101 ... ..... ..... \
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@rprr_scatter_store xs=2 esz=3 scale=1
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# SVE 64-bit scatter store (scalar plus 64-bit unscaled offset)
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ST1_zprz 1110010 .. 00 ..... 101 ... ..... ..... \
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@rprr_scatter_store xs=2 esz=3 scale=0
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# SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offset)
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# Require msz > 0
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ST1_zprz 1110010 .. 01 ..... 100 ... ..... ..... \
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@rprr_scatter_store xs=0 esz=3 scale=1
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ST1_zprz 1110010 .. 01 ..... 110 ... ..... ..... \
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@rprr_scatter_store xs=1 esz=3 scale=1
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# SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offset)
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ST1_zprz 1110010 .. 00 ..... 100 ... ..... ..... \
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@rprr_scatter_store xs=0 esz=3 scale=0
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ST1_zprz 1110010 .. 00 ..... 110 ... ..... ..... \
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@rprr_scatter_store xs=1 esz=3 scale=0
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@ -3713,3 +3713,64 @@ void HELPER(sve_st4dd_r)(CPUARMState *env, void *vg,
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addr += 4 * 8;
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}
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}
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/* Stores with a vector index. */
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#define DO_ST1_ZPZ_S(NAME, TYPEI, FN) \
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void HELPER(NAME)(CPUARMState *env, void *vd, void *vg, void *vm, \
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target_ulong base, uint32_t desc) \
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{ \
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intptr_t i, oprsz = simd_oprsz(desc); \
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unsigned scale = simd_data(desc); \
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uintptr_t ra = GETPC(); \
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for (i = 0; i < oprsz; ) { \
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uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3)); \
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do { \
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if (likely(pg & 1)) { \
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target_ulong off = *(TYPEI *)(vm + H1_4(i)); \
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uint32_t d = *(uint32_t *)(vd + H1_4(i)); \
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FN(env, base + (off << scale), d, ra); \
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} \
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i += sizeof(uint32_t), pg >>= sizeof(uint32_t); \
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} while (i & 15); \
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} \
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}
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#define DO_ST1_ZPZ_D(NAME, TYPEI, FN) \
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void HELPER(NAME)(CPUARMState *env, void *vd, void *vg, void *vm, \
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target_ulong base, uint32_t desc) \
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{ \
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intptr_t i, oprsz = simd_oprsz(desc) / 8; \
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unsigned scale = simd_data(desc); \
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uintptr_t ra = GETPC(); \
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uint64_t *d = vd, *m = vm; uint8_t *pg = vg; \
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for (i = 0; i < oprsz; i++) { \
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if (likely(pg[H1(i)] & 1)) { \
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target_ulong off = (target_ulong)(TYPEI)m[i] << scale; \
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FN(env, base + off, d[i], ra); \
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} \
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} \
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}
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DO_ST1_ZPZ_S(sve_stbs_zsu, uint32_t, cpu_stb_data_ra)
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DO_ST1_ZPZ_S(sve_sths_zsu, uint32_t, cpu_stw_data_ra)
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DO_ST1_ZPZ_S(sve_stss_zsu, uint32_t, cpu_stl_data_ra)
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DO_ST1_ZPZ_S(sve_stbs_zss, int32_t, cpu_stb_data_ra)
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DO_ST1_ZPZ_S(sve_sths_zss, int32_t, cpu_stw_data_ra)
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DO_ST1_ZPZ_S(sve_stss_zss, int32_t, cpu_stl_data_ra)
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DO_ST1_ZPZ_D(sve_stbd_zsu, uint32_t, cpu_stb_data_ra)
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DO_ST1_ZPZ_D(sve_sthd_zsu, uint32_t, cpu_stw_data_ra)
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DO_ST1_ZPZ_D(sve_stsd_zsu, uint32_t, cpu_stl_data_ra)
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DO_ST1_ZPZ_D(sve_stdd_zsu, uint32_t, cpu_stq_data_ra)
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DO_ST1_ZPZ_D(sve_stbd_zss, int32_t, cpu_stb_data_ra)
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DO_ST1_ZPZ_D(sve_sthd_zss, int32_t, cpu_stw_data_ra)
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DO_ST1_ZPZ_D(sve_stsd_zss, int32_t, cpu_stl_data_ra)
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DO_ST1_ZPZ_D(sve_stdd_zss, int32_t, cpu_stq_data_ra)
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DO_ST1_ZPZ_D(sve_stbd_zd, uint64_t, cpu_stb_data_ra)
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DO_ST1_ZPZ_D(sve_sthd_zd, uint64_t, cpu_stw_data_ra)
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DO_ST1_ZPZ_D(sve_stsd_zd, uint64_t, cpu_stl_data_ra)
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DO_ST1_ZPZ_D(sve_stdd_zd, uint64_t, cpu_stq_data_ra)
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@ -43,6 +43,8 @@ typedef void gen_helper_gvec_flags_4(TCGv_i32, TCGv_ptr, TCGv_ptr,
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TCGv_ptr, TCGv_ptr, TCGv_i32);
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typedef void gen_helper_gvec_mem(TCGv_env, TCGv_ptr, TCGv_i64, TCGv_i32);
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typedef void gen_helper_gvec_mem_scatter(TCGv_env, TCGv_ptr, TCGv_ptr,
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TCGv_ptr, TCGv_i64, TCGv_i32);
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/*
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* Helpers for extracting complex instruction fields.
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@ -4228,3 +4230,76 @@ static bool trans_ST_zpri(DisasContext *s, arg_rpri_store *a, uint32_t insn)
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}
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return true;
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}
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/*
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*** SVE gather loads / scatter stores
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*/
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static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm, int scale,
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TCGv_i64 scalar, gen_helper_gvec_mem_scatter *fn)
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{
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unsigned vsz = vec_full_reg_size(s);
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TCGv_i32 desc = tcg_const_i32(simd_desc(vsz, vsz, scale));
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TCGv_ptr t_zm = tcg_temp_new_ptr();
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TCGv_ptr t_pg = tcg_temp_new_ptr();
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TCGv_ptr t_zt = tcg_temp_new_ptr();
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tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
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tcg_gen_addi_ptr(t_zm, cpu_env, vec_full_reg_offset(s, zm));
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tcg_gen_addi_ptr(t_zt, cpu_env, vec_full_reg_offset(s, zt));
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fn(cpu_env, t_zt, t_pg, t_zm, scalar, desc);
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tcg_temp_free_ptr(t_zt);
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tcg_temp_free_ptr(t_zm);
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tcg_temp_free_ptr(t_pg);
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tcg_temp_free_i32(desc);
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}
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static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a, uint32_t insn)
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{
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/* Indexed by [xs][msz]. */
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static gen_helper_gvec_mem_scatter * const fn32[2][3] = {
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{ gen_helper_sve_stbs_zsu,
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gen_helper_sve_sths_zsu,
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gen_helper_sve_stss_zsu, },
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{ gen_helper_sve_stbs_zss,
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gen_helper_sve_sths_zss,
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gen_helper_sve_stss_zss, },
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};
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/* Note that we overload xs=2 to indicate 64-bit offset. */
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static gen_helper_gvec_mem_scatter * const fn64[3][4] = {
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{ gen_helper_sve_stbd_zsu,
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gen_helper_sve_sthd_zsu,
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gen_helper_sve_stsd_zsu,
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gen_helper_sve_stdd_zsu, },
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{ gen_helper_sve_stbd_zss,
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gen_helper_sve_sthd_zss,
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gen_helper_sve_stsd_zss,
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gen_helper_sve_stdd_zss, },
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{ gen_helper_sve_stbd_zd,
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gen_helper_sve_sthd_zd,
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gen_helper_sve_stsd_zd,
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gen_helper_sve_stdd_zd, },
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};
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gen_helper_gvec_mem_scatter *fn;
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if (a->esz < a->msz || (a->msz == 0 && a->scale)) {
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return false;
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}
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if (!sve_access_check(s)) {
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return true;
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}
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switch (a->esz) {
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case MO_32:
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fn = fn32[a->xs][a->msz];
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break;
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case MO_64:
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fn = fn64[a->xs][a->msz];
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break;
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default:
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g_assert_not_reached();
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}
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do_mem_zpz(s, a->rd, a->pg, a->rm, a->scale * a->msz,
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cpu_reg_sp(s, a->rn), fn);
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return true;
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}
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