mirror of https://github.com/xemu-project/xemu.git
target/arm: Add GPC syndrome
The function takes the fields as filled in by the Arm ARM pseudocode for TakeGPCException. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230620124418.805717-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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target/arm
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@ -50,6 +50,7 @@ enum arm_exception_class {
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EC_SVEACCESSTRAP = 0x19,
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EC_ERETTRAP = 0x1a,
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EC_SMETRAP = 0x1d,
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EC_GPC = 0x1e,
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EC_INSNABORT = 0x20,
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EC_INSNABORT_SAME_EL = 0x21,
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EC_PCALIGNMENT = 0x22,
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@ -247,6 +248,15 @@ static inline uint32_t syn_bxjtrap(int cv, int cond, int rm)
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(cv << 24) | (cond << 20) | rm;
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}
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static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc,
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int cm, int s1ptw, int wnr, int fsc)
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{
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/* TODO: FEAT_NV2 adds VNCR */
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return (EC_GPC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (s2ptw << 21)
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| (ind << 20) | (gpcsc << 14) | (cm << 8) | (s1ptw << 7)
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| (wnr << 6) | fsc;
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}
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static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
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{
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return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
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