mirror of https://github.com/xemu-project/xemu.git
target/ppc: implement vgnb
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-19-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Matheus Ferst
Cédric Le Goater
parent
95f1ee288b
commit
f622ebe7a5
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@ -66,6 +66,9 @@
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&VX_mp rt mp:bool vrb
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&VX_mp rt mp:bool vrb
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@VX_mp ...... rt:5 .... mp:1 vrb:5 ........... &VX_mp
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@VX_mp ...... rt:5 .... mp:1 vrb:5 ........... &VX_mp
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&VX_n rt vrb n
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@VX_n ...... rt:5 .. n:3 vrb:5 ........... &VX_n
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&VX_tb_rc vrt vrb rc:bool
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&VX_tb_rc vrt vrb rc:bool
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@VX_tb_rc ...... vrt:5 ..... vrb:5 rc:1 .......... &VX_tb_rc
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@VX_tb_rc ...... vrt:5 ..... vrb:5 rc:1 .......... &VX_tb_rc
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@ -418,6 +421,8 @@ VCMPUQ 000100 ... -- ..... ..... 00100000001 @VX_bf
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## Vector Bit Manipulation Instruction
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## Vector Bit Manipulation Instruction
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VGNB 000100 ..... -- ... ..... 10011001100 @VX_n
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VCFUGED 000100 ..... ..... ..... 10101001101 @VX
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VCFUGED 000100 ..... ..... ..... 10101001101 @VX
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VCLZDM 000100 ..... ..... ..... 11110000100 @VX
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VCLZDM 000100 ..... ..... ..... 11110000100 @VX
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VCTZDM 000100 ..... ..... ..... 11111000100 @VX
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VCTZDM 000100 ..... ..... ..... 11111000100 @VX
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@ -1416,6 +1416,141 @@ GEN_VXFORM_DUAL(vsplth, PPC_ALTIVEC, PPC_NONE,
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GEN_VXFORM_DUAL(vspltw, PPC_ALTIVEC, PPC_NONE,
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GEN_VXFORM_DUAL(vspltw, PPC_ALTIVEC, PPC_NONE,
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vextractuw, PPC_NONE, PPC2_ISA300);
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vextractuw, PPC_NONE, PPC2_ISA300);
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static bool trans_VGNB(DisasContext *ctx, arg_VX_n *a)
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{
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/*
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* Similar to do_vextractm, we'll use a sequence of mask-shift-or operations
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* to gather the bits. The masks can be created with
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*
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* uint64_t mask(uint64_t n, uint64_t step)
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* {
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* uint64_t p = ((1UL << (1UL << step)) - 1UL) << ((n - 1UL) << step),
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* plen = n << step, m = 0;
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* for(int i = 0; i < 64/plen; i++) {
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* m |= p;
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* m = ror64(m, plen);
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* }
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* p >>= plen * DIV_ROUND_UP(64, plen) - 64;
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* return m | p;
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* }
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*
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* But since there are few values of N, we'll use a lookup table to avoid
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* these calculations at runtime.
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*/
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static const uint64_t mask[6][5] = {
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{
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0xAAAAAAAAAAAAAAAAULL, 0xccccccccccccccccULL, 0xf0f0f0f0f0f0f0f0ULL,
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0xff00ff00ff00ff00ULL, 0xffff0000ffff0000ULL
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},
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{
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0x9249249249249249ULL, 0xC30C30C30C30C30CULL, 0xF00F00F00F00F00FULL,
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0xFF0000FF0000FF00ULL, 0xFFFF00000000FFFFULL
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},
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{
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/* For N >= 4, some mask operations can be elided */
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0x8888888888888888ULL, 0, 0xf000f000f000f000ULL, 0,
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0xFFFF000000000000ULL
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},
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{
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0x8421084210842108ULL, 0, 0xF0000F0000F0000FULL, 0, 0
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},
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{
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0x8208208208208208ULL, 0, 0xF00000F00000F000ULL, 0, 0
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},
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{
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0x8102040810204081ULL, 0, 0xF000000F000000F0ULL, 0, 0
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}
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};
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uint64_t m;
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int i, sh, nbits = DIV_ROUND_UP(64, a->n);
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TCGv_i64 hi, lo, t0, t1;
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REQUIRE_INSNS_FLAGS2(ctx, ISA310);
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REQUIRE_VECTOR(ctx);
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if (a->n < 2) {
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/*
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* "N can be any value between 2 and 7, inclusive." Otherwise, the
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* result is undefined, so we don't need to change RT. Also, N > 7 is
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* impossible since the immediate field is 3 bits only.
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*/
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return true;
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}
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hi = tcg_temp_new_i64();
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lo = tcg_temp_new_i64();
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t0 = tcg_temp_new_i64();
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t1 = tcg_temp_new_i64();
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get_avr64(hi, a->vrb, true);
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get_avr64(lo, a->vrb, false);
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/* Align the lower doubleword so we can use the same mask */
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tcg_gen_shli_i64(lo, lo, a->n * nbits - 64);
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/*
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* Starting from the most significant bit, gather every Nth bit with a
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* sequence of mask-shift-or operation. E.g.: for N=3
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* AxxBxxCxxDxxExxFxxGxxHxxIxxJxxKxxLxxMxxNxxOxxPxxQxxRxxSxxTxxUxxV
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* & rep(0b100)
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* A..B..C..D..E..F..G..H..I..J..K..L..M..N..O..P..Q..R..S..T..U..V
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* << 2
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* .B..C..D..E..F..G..H..I..J..K..L..M..N..O..P..Q..R..S..T..U..V..
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* |
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* AB.BC.CD.DE.EF.FG.GH.HI.IJ.JK.KL.LM.MN.NO.OP.PQ.QR.RS.ST.TU.UV.V
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* & rep(0b110000)
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* AB....CD....EF....GH....IJ....KL....MN....OP....QR....ST....UV..
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* << 4
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* ..CD....EF....GH....IJ....KL....MN....OP....QR....ST....UV......
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* |
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* ABCD..CDEF..EFGH..GHIJ..IJKL..KLMN..MNOP..OPQR..QRST..STUV..UV..
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* & rep(0b111100000000)
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* ABCD........EFGH........IJKL........MNOP........QRST........UV..
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* << 8
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* ....EFGH........IJKL........MNOP........QRST........UV..........
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* |
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* ABCDEFGH....EFGHIJKL....IJKLMNOP....MNOPQRST....QRSTUV......UV..
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* & rep(0b111111110000000000000000)
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* ABCDEFGH................IJKLMNOP................QRSTUV..........
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* << 16
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* ........IJKLMNOP................QRSTUV..........................
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* |
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* ABCDEFGHIJKLMNOP........IJKLMNOPQRSTUV..........QRSTUV..........
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* & rep(0b111111111111111100000000000000000000000000000000)
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* ABCDEFGHIJKLMNOP................................QRSTUV..........
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* << 32
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* ................QRSTUV..........................................
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* |
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* ABCDEFGHIJKLMNOPQRSTUV..........................QRSTUV..........
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*/
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for (i = 0, sh = a->n - 1; i < 5; i++, sh <<= 1) {
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m = mask[a->n - 2][i];
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if (m) {
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tcg_gen_andi_i64(hi, hi, m);
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tcg_gen_andi_i64(lo, lo, m);
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}
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if (sh < 64) {
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tcg_gen_shli_i64(t0, hi, sh);
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tcg_gen_shli_i64(t1, lo, sh);
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tcg_gen_or_i64(hi, t0, hi);
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tcg_gen_or_i64(lo, t1, lo);
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}
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}
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tcg_gen_andi_i64(hi, hi, ~(~0ULL >> nbits));
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tcg_gen_andi_i64(lo, lo, ~(~0ULL >> nbits));
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tcg_gen_shri_i64(lo, lo, nbits);
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tcg_gen_or_i64(hi, hi, lo);
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tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], hi);
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tcg_temp_free_i64(hi);
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tcg_temp_free_i64(lo);
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t1);
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return true;
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}
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static bool do_vextdx(DisasContext *ctx, arg_VA *a, int size, bool right,
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static bool do_vextdx(DisasContext *ctx, arg_VA *a, int size, bool right,
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void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv))
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void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv))
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{
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{
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