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target/arm: Implement new VFP fp16 insn VMOVX 

The fp16 extension includes a new instruction VMOVX, which copies the
upper 16 bits of a 32-bit source VFP register into the lower 16
bits of the destination and zeroes the high half of the destination.
Implement it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-21-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-08-28 19:33:29 +01:00
parent e4875e3bcc
commit f61e5c43b8
2 changed files with 28 additions and 0 deletions
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25
target/arm/translate-vfp.c.inc
View File

@ -3482,3 +3482,28 @@ static bool trans_VINS(DisasContext *s, arg_VINS *a)
tcg_temp_free_i32(rd);
return true;
}
static bool trans_VMOVX(DisasContext *s, arg_VINS *a)
{
TCGv_i32 rm;
if (!dc_isar_feature(aa32_fp16_arith, s)) {
return false;
}
if (s->vec_len != 0 || s->vec_stride != 0) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
/* Set Vd to high half of Vm */
rm = tcg_temp_new_i32();
neon_load_reg32(rm, a->vm);
tcg_gen_shri_i32(rm, rm, 16);
neon_store_reg32(rm, a->vd);
tcg_temp_free_i32(rm);
return true;
}

3
target/arm/vfp-uncond.decode
View File

@ -75,5 +75,8 @@ VCVT 1111 1110 1.11 11 rm:2 .... 1010 op:1 1.0 .... \
VCVT 1111 1110 1.11 11 rm:2 .... 1011 op:1 1.0 .... \
vm=%vm_dp vd=%vd_sp sz=3
VMOVX 1111 1110 1.11 0000 .... 1010 01 . 0 .... \
vd=%vd_sp vm=%vm_sp
VINS 1111 1110 1.11 0000 .... 1010 11 . 0 .... \
vd=%vd_sp vm=%vm_sp