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ppc/ppc405: Add some address space definitions 

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211206103712.1866296-8-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Cédric Le Goater 2021-12-17 17:57:17 +01:00
parent a3e973e1bf
commit f61b99d35e
2 changed files with 14 additions and 9 deletions
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7
hw/ppc/ppc405.h
View File

@ -27,6 +27,13 @@
#include "hw/ppc/ppc4xx.h" #include "hw/ppc/ppc4xx.h"
#define PPC405EP_SDRAM_BASE 0x00000000
#define PPC405EP_NVRAM_BASE 0xF0000000
#define PPC405EP_FPGA_BASE 0xF0300000
#define PPC405EP_SRAM_BASE 0xFFF00000
#define PPC405EP_SRAM_SIZE (512 * KiB)
#define PPC405EP_FLASH_BASE 0xFFF80000
/* Bootinfo as set-up by u-boot */ /* Bootinfo as set-up by u-boot */
typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t; typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t;
struct ppc4xx_bd_info_t { struct ppc4xx_bd_info_t {

16
hw/ppc/ppc405_boards.c
View File

@ -154,7 +154,6 @@ static void ref405ep_init(MachineState *machine)
ram_addr_t bdloc; ram_addr_t bdloc;
MemoryRegion *ram_memories = g_new(MemoryRegion, 2); MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
hwaddr ram_bases[2], ram_sizes[2]; hwaddr ram_bases[2], ram_sizes[2];
target_ulong sram_size;
long bios_size; long bios_size;
//int phy_addr = 0; //int phy_addr = 0;
//static int phy_addr = 1; //static int phy_addr = 1;
@ -187,10 +186,9 @@ static void ref405ep_init(MachineState *machine)
env = &cpu->env; env = &cpu->env;
/* allocate SRAM */ /* allocate SRAM */
sram_size = 512 * KiB; memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE,
memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size,
&error_fatal); &error_fatal);
memory_region_add_subregion(sysmem, 0xFFF00000, sram); memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram);
/* allocate and load BIOS */ /* allocate and load BIOS */
#ifdef USE_FLASH_BIOS #ifdef USE_FLASH_BIOS
dinfo = drive_get(IF_PFLASH, 0, 0); dinfo = drive_get(IF_PFLASH, 0, 0);
@ -230,24 +228,24 @@ static void ref405ep_init(MachineState *machine)
} }
} }
/* Register FPGA */ /* Register FPGA */
ref405ep_fpga_init(sysmem, 0xF0300000); ref405ep_fpga_init(sysmem, PPC405EP_FPGA_BASE);
/* Register NVRAM */ /* Register NVRAM */
dev = qdev_new("sysbus-m48t08"); dev = qdev_new("sysbus-m48t08");
qdev_prop_set_int32(dev, "base-year", 1968); qdev_prop_set_int32(dev, "base-year", 1968);
s = SYS_BUS_DEVICE(dev); s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal); sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, 0xF0000000); sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE);
/* Load kernel */ /* Load kernel */
linux_boot = (kernel_filename != NULL); linux_boot = (kernel_filename != NULL);
if (linux_boot) { if (linux_boot) {
memset(&bd, 0, sizeof(bd)); memset(&bd, 0, sizeof(bd));
bd.bi_memstart = 0x00000000; bd.bi_memstart = PPC405EP_SDRAM_BASE;
bd.bi_memsize = machine->ram_size; bd.bi_memsize = machine->ram_size;
bd.bi_flashstart = -bios_size; bd.bi_flashstart = -bios_size;
bd.bi_flashsize = -bios_size; bd.bi_flashsize = -bios_size;
bd.bi_flashoffset = 0; bd.bi_flashoffset = 0;
bd.bi_sramstart = 0xFFF00000; bd.bi_sramstart = PPC405EP_SRAM_BASE;
bd.bi_sramsize = sram_size; bd.bi_sramsize = PPC405EP_SRAM_SIZE;
bd.bi_bootflags = 0; bd.bi_bootflags = 0;
bd.bi_intfreq = 133333333; bd.bi_intfreq = 133333333;
bd.bi_busfreq = 33333333; bd.bi_busfreq = 33333333;