mirror of https://github.com/xemu-project/xemu.git
hw/arm: Add 'virt' platform
Add 'virt' platform support corresponding to arch/arm/mach-virt in the Linux kernel tree. This has no platform-specific code but can use any device whose kernel driver is is able to work purely from a device tree node. We use this to instantiate a minimal set of devices: a GIC and some virtio-mmio transports. Signed-off-by: John Rigby <john.rigby@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1385140638-10444-8-git-send-email-peter.maydell@linaro.org [PMM: Significantly overhauled: * renamed user-facing machine to just "virt" * removed the A9 support (it can't work since the A9 has no generic timers) * added virtio-mmio transports instead of random set of 'soc' devices (though we retain a pl011 UART) * instead of updating io_base as we step through adding devices, define a memory map with an array (similar to vexpress) * similarly, define irqmap with an array * folded in some minor fixes from John's aarch64-support patch * rather than explicitly doing endian-swapping on FDT cells, use fdt APIs that let us just pass in host-endian values and let the fdt layer take care of the swapping * miscellaneous minor code cleanups and style fixes ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
parent
5de164304a
commit
f5fdcd6e58
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@ -1,7 +1,7 @@
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obj-y += boot.o collie.o exynos4_boards.o gumstix.o highbank.o
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obj-y += integratorcp.o kzm.o mainstone.o musicpal.o nseries.o
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obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o
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obj-y += tosa.o versatilepb.o vexpress.o xilinx_zynq.o z2.o
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obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
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obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
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obj-y += omap1.o omap2.o strongarm.o
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@ -0,0 +1,444 @@
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/*
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* ARM mach-virt emulation
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*
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* Copyright (c) 2013 Linaro Limited
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Emulate a virtual board which works by passing Linux all the information
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* it needs about what devices are present via the device tree.
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* There are some restrictions about what we can do here:
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* + we can only present devices whose Linux drivers will work based
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* purely on the device tree with no platform data at all
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* + we want to present a very stripped-down minimalist platform,
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* both because this reduces the security attack surface from the guest
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* and also because it reduces our exposure to being broken when
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* the kernel updates its device tree bindings and requires further
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* information in a device binding that we aren't providing.
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* This is essentially the same approach kvmtool uses.
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*/
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#include "hw/sysbus.h"
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#include "hw/arm/arm.h"
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#include "hw/arm/primecell.h"
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#include "hw/devices.h"
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#include "net/net.h"
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#include "sysemu/device_tree.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/kvm.h"
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#include "hw/boards.h"
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#include "exec/address-spaces.h"
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#include "qemu/bitops.h"
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#include "qemu/error-report.h"
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#define NUM_VIRTIO_TRANSPORTS 32
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/* Number of external interrupt lines to configure the GIC with */
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#define NUM_IRQS 128
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#define GIC_FDT_IRQ_TYPE_SPI 0
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#define GIC_FDT_IRQ_TYPE_PPI 1
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#define GIC_FDT_IRQ_FLAGS_EDGE_LO_HI 1
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#define GIC_FDT_IRQ_FLAGS_EDGE_HI_LO 2
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#define GIC_FDT_IRQ_FLAGS_LEVEL_HI 4
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#define GIC_FDT_IRQ_FLAGS_LEVEL_LO 8
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#define GIC_FDT_IRQ_PPI_CPU_START 8
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#define GIC_FDT_IRQ_PPI_CPU_WIDTH 8
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enum {
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VIRT_FLASH,
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VIRT_MEM,
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VIRT_CPUPERIPHS,
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VIRT_GIC_DIST,
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VIRT_GIC_CPU,
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VIRT_UART,
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VIRT_MMIO,
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};
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typedef struct MemMapEntry {
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hwaddr base;
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hwaddr size;
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} MemMapEntry;
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typedef struct VirtBoardInfo {
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struct arm_boot_info bootinfo;
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const char *cpu_model;
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const char *qdevname;
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const char *gic_compatible;
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const MemMapEntry *memmap;
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const int *irqmap;
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int smp_cpus;
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void *fdt;
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int fdt_size;
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uint32_t clock_phandle;
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} VirtBoardInfo;
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/* Addresses and sizes of our components.
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* 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
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* 128MB..256MB is used for miscellaneous device I/O.
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* 256MB..1GB is reserved for possible future PCI support (ie where the
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* PCI memory window will go if we add a PCI host controller).
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* 1GB and up is RAM (which may happily spill over into the
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* high memory region beyond 4GB).
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* This represents a compromise between how much RAM can be given to
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* a 32 bit VM and leaving space for expansion and in particular for PCI.
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*/
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static const MemMapEntry a15memmap[] = {
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/* Space up to 0x8000000 is reserved for a boot ROM */
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[VIRT_FLASH] = { 0, 0x8000000 },
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[VIRT_CPUPERIPHS] = { 0x8000000, 0x8000 },
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/* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
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[VIRT_GIC_DIST] = { 0x8001000, 0x1000 },
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[VIRT_GIC_CPU] = { 0x8002000, 0x1000 },
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[VIRT_UART] = { 0x9000000, 0x1000 },
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[VIRT_MMIO] = { 0xa000000, 0x200 },
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/* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
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/* 0x10000000 .. 0x40000000 reserved for PCI */
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[VIRT_MEM] = { 0x40000000, 30ULL * 1024 * 1024 * 1024 },
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};
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static const int a15irqmap[] = {
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[VIRT_UART] = 1,
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[VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
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};
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static VirtBoardInfo machines[] = {
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{
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.cpu_model = "cortex-a15",
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.qdevname = "a15mpcore_priv",
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.gic_compatible = "arm,cortex-a15-gic",
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.memmap = a15memmap,
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.irqmap = a15irqmap,
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},
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};
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static VirtBoardInfo *find_machine_info(const char *cpu)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(machines); i++) {
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if (strcmp(cpu, machines[i].cpu_model) == 0) {
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return &machines[i];
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}
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}
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return NULL;
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}
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static void create_fdt(VirtBoardInfo *vbi)
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{
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void *fdt = create_device_tree(&vbi->fdt_size);
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if (!fdt) {
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error_report("create_device_tree() failed");
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exit(1);
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}
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vbi->fdt = fdt;
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/* Header */
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qemu_devtree_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
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qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 0x2);
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qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 0x2);
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/*
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* /chosen and /memory nodes must exist for load_dtb
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* to fill in necessary properties later
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*/
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qemu_devtree_add_subnode(fdt, "/chosen");
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qemu_devtree_add_subnode(fdt, "/memory");
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qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory");
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/* Clock node, for the benefit of the UART. The kernel device tree
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* binding documentation claims the PL011 node clock properties are
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* optional but in practice if you omit them the kernel refuses to
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* probe for the device.
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*/
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vbi->clock_phandle = qemu_devtree_alloc_phandle(fdt);
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qemu_devtree_add_subnode(fdt, "/apb-pclk");
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qemu_devtree_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
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qemu_devtree_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
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qemu_devtree_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
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qemu_devtree_setprop_string(fdt, "/apb-pclk", "clock-output-names",
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"clk24mhz");
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qemu_devtree_setprop_cell(fdt, "/apb-pclk", "phandle", vbi->clock_phandle);
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/* No PSCI for TCG yet */
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if (kvm_enabled()) {
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qemu_devtree_add_subnode(fdt, "/psci");
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qemu_devtree_setprop_string(fdt, "/psci", "compatible", "arm,psci");
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qemu_devtree_setprop_string(fdt, "/psci", "method", "hvc");
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qemu_devtree_setprop_cell(fdt, "/psci", "cpu_suspend",
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PSCI_FN_CPU_SUSPEND);
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qemu_devtree_setprop_cell(fdt, "/psci", "cpu_off", PSCI_FN_CPU_OFF);
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qemu_devtree_setprop_cell(fdt, "/psci", "cpu_on", PSCI_FN_CPU_ON);
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qemu_devtree_setprop_cell(fdt, "/psci", "migrate", PSCI_FN_MIGRATE);
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}
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}
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static void fdt_add_timer_nodes(const VirtBoardInfo *vbi)
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{
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/* Note that on A15 h/w these interrupts are level-triggered,
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* but for the GIC implementation provided by both QEMU and KVM
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* they are edge-triggered.
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*/
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uint32_t irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
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irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
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GIC_FDT_IRQ_PPI_CPU_WIDTH, (1 << vbi->smp_cpus) - 1);
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qemu_devtree_add_subnode(vbi->fdt, "/timer");
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qemu_devtree_setprop_string(vbi->fdt, "/timer",
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"compatible", "arm,armv7-timer");
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qemu_devtree_setprop_cells(vbi->fdt, "/timer", "interrupts",
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GIC_FDT_IRQ_TYPE_PPI, 13, irqflags,
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GIC_FDT_IRQ_TYPE_PPI, 14, irqflags,
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GIC_FDT_IRQ_TYPE_PPI, 11, irqflags,
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GIC_FDT_IRQ_TYPE_PPI, 10, irqflags);
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}
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static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi)
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{
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int cpu;
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qemu_devtree_add_subnode(vbi->fdt, "/cpus");
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qemu_devtree_setprop_cell(vbi->fdt, "/cpus", "#address-cells", 0x1);
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qemu_devtree_setprop_cell(vbi->fdt, "/cpus", "#size-cells", 0x0);
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for (cpu = vbi->smp_cpus - 1; cpu >= 0; cpu--) {
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char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
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ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
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qemu_devtree_add_subnode(vbi->fdt, nodename);
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qemu_devtree_setprop_string(vbi->fdt, nodename, "device_type", "cpu");
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qemu_devtree_setprop_string(vbi->fdt, nodename, "compatible",
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armcpu->dtb_compatible);
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if (vbi->smp_cpus > 1) {
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qemu_devtree_setprop_string(vbi->fdt, nodename,
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"enable-method", "psci");
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}
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qemu_devtree_setprop_cell(vbi->fdt, nodename, "reg", cpu);
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g_free(nodename);
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}
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}
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static void fdt_add_gic_node(const VirtBoardInfo *vbi)
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{
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uint32_t gic_phandle;
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gic_phandle = qemu_devtree_alloc_phandle(vbi->fdt);
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qemu_devtree_setprop_cell(vbi->fdt, "/", "interrupt-parent", gic_phandle);
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qemu_devtree_add_subnode(vbi->fdt, "/intc");
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qemu_devtree_setprop_string(vbi->fdt, "/intc", "compatible",
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vbi->gic_compatible);
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qemu_devtree_setprop_cell(vbi->fdt, "/intc", "#interrupt-cells", 3);
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qemu_devtree_setprop(vbi->fdt, "/intc", "interrupt-controller", NULL, 0);
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qemu_devtree_setprop_sized_cells(vbi->fdt, "/intc", "reg",
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2, vbi->memmap[VIRT_GIC_DIST].base,
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2, vbi->memmap[VIRT_GIC_DIST].size,
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2, vbi->memmap[VIRT_GIC_CPU].base,
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2, vbi->memmap[VIRT_GIC_CPU].size);
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qemu_devtree_setprop_cell(vbi->fdt, "/intc", "phandle", gic_phandle);
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}
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static void create_uart(const VirtBoardInfo *vbi, qemu_irq *pic)
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{
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char *nodename;
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hwaddr base = vbi->memmap[VIRT_UART].base;
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hwaddr size = vbi->memmap[VIRT_UART].size;
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int irq = vbi->irqmap[VIRT_UART];
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const char compat[] = "arm,pl011\0arm,primecell";
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const char clocknames[] = "uartclk\0apb_pclk";
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sysbus_create_simple("pl011", base, pic[irq]);
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nodename = g_strdup_printf("/pl011@%" PRIx64, base);
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qemu_devtree_add_subnode(vbi->fdt, nodename);
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/* Note that we can't use setprop_string because of the embedded NUL */
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qemu_devtree_setprop(vbi->fdt, nodename, "compatible",
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compat, sizeof(compat));
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qemu_devtree_setprop_sized_cells(vbi->fdt, nodename, "reg",
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2, base, 2, size);
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qemu_devtree_setprop_cells(vbi->fdt, nodename, "interrupts",
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GIC_FDT_IRQ_TYPE_SPI, irq,
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GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
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qemu_devtree_setprop_cells(vbi->fdt, nodename, "clocks",
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vbi->clock_phandle, vbi->clock_phandle);
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qemu_devtree_setprop(vbi->fdt, nodename, "clock-names",
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clocknames, sizeof(clocknames));
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g_free(nodename);
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}
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static void create_virtio_devices(const VirtBoardInfo *vbi, qemu_irq *pic)
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{
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int i;
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hwaddr size = vbi->memmap[VIRT_MMIO].size;
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/* Note that we have to create the transports in forwards order
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* so that command line devices are inserted lowest address first,
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* and then add dtb nodes in reverse order so that they appear in
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* the finished device tree lowest address first.
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*/
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for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
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int irq = vbi->irqmap[VIRT_MMIO] + i;
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hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size;
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sysbus_create_simple("virtio-mmio", base, pic[irq]);
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}
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for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
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char *nodename;
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int irq = vbi->irqmap[VIRT_MMIO] + i;
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hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size;
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nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
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qemu_devtree_add_subnode(vbi->fdt, nodename);
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qemu_devtree_setprop_string(vbi->fdt, nodename,
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"compatible", "virtio,mmio");
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qemu_devtree_setprop_sized_cells(vbi->fdt, nodename, "reg",
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2, base, 2, size);
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qemu_devtree_setprop_cells(vbi->fdt, nodename, "interrupts",
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GIC_FDT_IRQ_TYPE_SPI, irq,
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GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
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g_free(nodename);
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}
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}
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static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
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{
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const VirtBoardInfo *board = (const VirtBoardInfo *)binfo;
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*fdt_size = board->fdt_size;
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return board->fdt;
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}
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static void machvirt_init(QEMUMachineInitArgs *args)
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{
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qemu_irq pic[NUM_IRQS];
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MemoryRegion *sysmem = get_system_memory();
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int n;
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MemoryRegion *ram = g_new(MemoryRegion, 1);
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DeviceState *dev;
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SysBusDevice *busdev;
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const char *cpu_model = args->cpu_model;
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VirtBoardInfo *vbi;
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if (!cpu_model) {
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cpu_model = "cortex-a15";
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}
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vbi = find_machine_info(cpu_model);
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if (!vbi) {
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error_report("mach-virt: CPU %s not supported", cpu_model);
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exit(1);
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}
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vbi->smp_cpus = smp_cpus;
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/*
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* Only supported method of starting secondary CPUs is PSCI and
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* PSCI is not yet supported with TCG, so limit smp_cpus to 1
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* if we're not using KVM.
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*/
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if (!kvm_enabled() && smp_cpus > 1) {
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error_report("mach-virt: must enable KVM to use multiple CPUs");
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exit(1);
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}
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if (args->ram_size > vbi->memmap[VIRT_MEM].size) {
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error_report("mach-virt: cannot model more than 30GB RAM");
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exit(1);
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}
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create_fdt(vbi);
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fdt_add_timer_nodes(vbi);
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for (n = 0; n < smp_cpus; n++) {
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ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
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Object *cpuobj;
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if (!oc) {
|
||||
fprintf(stderr, "Unable to find CPU definition\n");
|
||||
exit(1);
|
||||
}
|
||||
cpuobj = object_new(object_class_get_name(oc));
|
||||
|
||||
/* Secondary CPUs start in PSCI powered-down state */
|
||||
if (n > 0) {
|
||||
object_property_set_bool(cpuobj, true, "start-powered-off", NULL);
|
||||
}
|
||||
object_property_set_bool(cpuobj, true, "realized", NULL);
|
||||
}
|
||||
fdt_add_cpu_nodes(vbi);
|
||||
|
||||
memory_region_init_ram(ram, NULL, "mach-virt.ram", args->ram_size);
|
||||
vmstate_register_ram_global(ram);
|
||||
memory_region_add_subregion(sysmem, vbi->memmap[VIRT_MEM].base, ram);
|
||||
|
||||
dev = qdev_create(NULL, vbi->qdevname);
|
||||
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
|
||||
/* Note that the num-irq property counts both internal and external
|
||||
* interrupts; there are always 32 of the former (mandated by GIC spec).
|
||||
*/
|
||||
qdev_prop_set_uint32(dev, "num-irq", NUM_IRQS + 32);
|
||||
qdev_init_nofail(dev);
|
||||
busdev = SYS_BUS_DEVICE(dev);
|
||||
sysbus_mmio_map(busdev, 0, vbi->memmap[VIRT_CPUPERIPHS].base);
|
||||
fdt_add_gic_node(vbi);
|
||||
for (n = 0; n < smp_cpus; n++) {
|
||||
DeviceState *cpudev = DEVICE(qemu_get_cpu(n));
|
||||
|
||||
sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
|
||||
}
|
||||
|
||||
for (n = 0; n < NUM_IRQS; n++) {
|
||||
pic[n] = qdev_get_gpio_in(dev, n);
|
||||
}
|
||||
|
||||
create_uart(vbi, pic);
|
||||
|
||||
/* Create mmio transports, so the user can create virtio backends
|
||||
* (which will be automatically plugged in to the transports). If
|
||||
* no backend is created the transport will just sit harmlessly idle.
|
||||
*/
|
||||
create_virtio_devices(vbi, pic);
|
||||
|
||||
vbi->bootinfo.ram_size = args->ram_size;
|
||||
vbi->bootinfo.kernel_filename = args->kernel_filename;
|
||||
vbi->bootinfo.kernel_cmdline = args->kernel_cmdline;
|
||||
vbi->bootinfo.initrd_filename = args->initrd_filename;
|
||||
vbi->bootinfo.nb_cpus = smp_cpus;
|
||||
vbi->bootinfo.board_id = -1;
|
||||
vbi->bootinfo.loader_start = vbi->memmap[VIRT_MEM].base;
|
||||
vbi->bootinfo.get_dtb = machvirt_dtb;
|
||||
arm_load_kernel(ARM_CPU(first_cpu), &vbi->bootinfo);
|
||||
}
|
||||
|
||||
static QEMUMachine machvirt_a15_machine = {
|
||||
.name = "virt",
|
||||
.desc = "ARM Virtual Machine",
|
||||
.init = machvirt_init,
|
||||
.max_cpus = 4,
|
||||
};
|
||||
|
||||
static void machvirt_machine_init(void)
|
||||
{
|
||||
qemu_register_machine(&machvirt_a15_machine);
|
||||
}
|
||||
|
||||
machine_init(machvirt_machine_init);
|
||||
Loading…
Reference in New Issue