mirror of https://github.com/xemu-project/xemu.git
MIPS + misc queue for June 15th, 2020
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJe58Z1AAoJENSXKoln91pls1gH/iONQAlW6ph6C3YGgJaOk6gi B5uAOz4ID5m50SHdraoJTpeg6K+9JLSGSxNBShcbxalfe5pu7aFCBflDQP8bUskS noXID/LC2KNhvFIZDjERQPK6aMzfvOpM0lmX7VlC+qm99SwHN4qH7W3vm035emjA f7cxGIyvSHlKmehnfUL92W8wKszdRkllB4zDYQDvBtEntbkEEvOIvRYaylXw5+/E 2hpG8MTH6bz8XFeBcBBePLw5ducKKeWTesHCjvUizGbmuzFcD3WgG1gtwHti6lc6 xNZelsLXKNGtIzreRKGa4dtEj2ncQsynKkYrWDKKDexXEbJbQZMAlw3umHpxP9w= =0x8C -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jun-15-2020' into staging MIPS + misc queue for June 15th, 2020 # gpg: Signature made Mon 15 Jun 2020 20:05:25 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [full] # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-jun-15-2020: translations: Add Swedish language MAINTAINERS: Adjust sh4 maintainership target/mips: msa: Split helpers for MULV.<B|H|W|D> target/mips: msa: Split helpers for SUBV.<B|H|W|D> target/mips: msa: Split helpers for SUBSUU_S.<B|H|W|D> target/mips: msa: Split helpers for SUBSUS_U.<B|H|W|D> target/mips: msa: Split helpers for SUBS_U.<B|H|W|D> target/mips: msa: Split helpers for SUBS_S.<B|H|W|D> target/mips: msa: Split helpers for DOTP_U.<H|W|D> target/mips: msa: Split helpers for DOTP_S.<H|W|D> target/mips: msa: Split helpers for DPSUB_U.<H|W|D> target/mips: msa: Split helpers for DPSUB_S.<H|W|D> target/mips: msa: Split helpers for DPADD_U.<H|W|D> target/mips: msa: Split helpers for DPADD_S.<H|W|D> target/mips: msa: Split helpers for MSUBV.<B|H|W|D> target/mips: msa: Split helpers for MADDV.<B|H|W|D> target/mips: Add comments for vendor-specific ASEs target/mips: Legalize Loongson insn flags Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
f5e34624f2
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@ -296,7 +296,7 @@ F: tests/tcg/s390x/
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L: qemu-s390x@nongnu.org
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SH4 TCG CPUs
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M: Aurelien Jarno <aurelien@aurel32.net>
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M: Yoshinori Sato <ysato@users.sourceforge.jp>
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S: Odd Fixes
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F: target/sh4/
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F: hw/sh4/
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@ -1253,14 +1253,16 @@ F: include/hw/riscv/opentitan.h
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SH4 Machines
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------------
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R2D
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M: Magnus Damm <magnus.damm@gmail.com>
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M: Yoshinori Sato <ysato@users.sourceforge.jp>
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R: Magnus Damm <magnus.damm@gmail.com>
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S: Maintained
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F: hw/sh4/r2d.c
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F: hw/intc/sh_intc.c
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F: hw/timer/sh_timer.c
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Shix
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M: Magnus Damm <magnus.damm@gmail.com>
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M: Yoshinori Sato <ysato@users.sourceforge.jp>
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R: Magnus Damm <magnus.damm@gmail.com>
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S: Odd Fixes
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F: hw/sh4/shix.c
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@ -0,0 +1,75 @@
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# Swedish translation of qemu po-file.
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# This file is put in the public domain.
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# Sebastian Rasmussen <sebras@gmail.com>, 2019.
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#
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msgid ""
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msgstr ""
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"Project-Id-Version: QEMU 2.12.91\n"
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"Report-Msgid-Bugs-To: qemu-devel@nongnu.org\n"
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"POT-Creation-Date: 2018-07-18 07:56+0200\n"
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"PO-Revision-Date: 2019-08-16 21:19+0200\n"
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"Last-Translator: Sebastian Rasmussen <sebras@gmail.com>\n"
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"Language-Team: Swedish <tp-sv@listor.tp-sv.se>\n"
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"Language: sv\n"
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"MIME-Version: 1.0\n"
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"Content-Type: text/plain; charset=UTF-8\n"
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"Content-Transfer-Encoding: 8bit\n"
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"Plural-Forms: nplurals=2; plural=(n != 1);\n"
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"X-Generator: Poedit 2.2.3\n"
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msgid " - Press Ctrl+Alt+G to release grab"
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msgstr " - Tryck Ctrl+Alt+G för att sluta fånga"
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msgid " [Paused]"
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msgstr " [Pausad]"
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msgid "_Pause"
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msgstr "_Paus"
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msgid "_Reset"
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msgstr "_Starta om"
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msgid "Power _Down"
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msgstr "Stäng _ner"
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msgid "_Quit"
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msgstr "_Avsluta"
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msgid "_Fullscreen"
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msgstr "_Helskärm"
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msgid "_Copy"
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msgstr "_Kopiera"
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msgid "Zoom _In"
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msgstr "Zooma _in"
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msgid "Zoom _Out"
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msgstr "Zooma _ut"
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msgid "Best _Fit"
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msgstr "Anpassad _storlek"
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msgid "Zoom To _Fit"
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msgstr "Zooma ti_ll anpassad storlek"
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msgid "Grab On _Hover"
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msgstr "Fånga vi_d hovring"
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msgid "_Grab Input"
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msgstr "Fån_ga inmatning"
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msgid "Show _Tabs"
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msgstr "Visa _flika"
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msgid "Detach Tab"
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msgstr "Frigör flik"
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msgid "Show Menubar"
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msgstr "Visa menyrad"
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msgid "_Machine"
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msgstr "_Maskin"
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msgid "_View"
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msgstr "_Visa"
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@ -950,6 +950,21 @@ DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_maddv_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_maddv_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_maddv_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_maddv_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_msubv_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_msubv_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_msubv_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_msubv_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_mulv_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_mulv_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_mulv_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_mulv_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_asub_s_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_asub_s_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_asub_s_w, void, env, i32, i32, i32)
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@ -968,6 +983,31 @@ DEF_HELPER_4(msa_hsub_u_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_hsub_u_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_hsub_u_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_subs_s_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_subs_s_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_subs_s_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_subs_s_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_subs_u_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_subs_u_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_subs_u_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_subs_u_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_subsus_u_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_subsus_u_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_subsus_u_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_subsus_u_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_subsuu_s_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_subsuu_s_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_subsuu_s_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_subsuu_s_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_subv_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_subv_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_subv_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_subv_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_ilvev_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_ilvev_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_ilvev_w, void, env, i32, i32, i32)
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@ -1063,20 +1103,25 @@ DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_subv_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_subs_s_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_subs_u_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_subsus_u_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_subsuu_s_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_mulv_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_maddv_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_msubv_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_dotp_s_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_dotp_u_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_dpadd_s_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_dpadd_u_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_dpsub_s_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_dpsub_u_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_4(msa_dotp_s_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_dotp_s_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_dotp_s_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_dotp_u_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_dotp_u_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_dotp_u_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_dpadd_s_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_dpadd_s_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_dpadd_s_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_dpadd_u_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_dpadd_u_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_dpadd_u_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_dpsub_s_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_dpsub_s_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_dpsub_s_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_dpsub_u_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_dpsub_u_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_dpsub_u_d, void, env, i32, i32, i32)
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DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32)
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@ -57,9 +57,13 @@
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/*
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* bits 52-63: vendor-specific ASEs
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*/
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/* MultiMedia Instructions defined by R5900 */
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#define ASE_MMI 0x0010000000000000ULL
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/* MIPS eXtension/enhanced Unit defined by Ingenic */
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#define ASE_MXU 0x0020000000000000ULL
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/* Loongson MultiMedia Instructions */
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#define ASE_LMMI 0x0040000000000000ULL
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/* Loongson EXTensions */
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#define ASE_LEXT 0x0080000000000000ULL
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/* MIPS CPU defines. */
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@ -70,7 +74,7 @@
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#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
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#define CPU_R5900 (CPU_MIPS3 | INSN_R5900)
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#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
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#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F)
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#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI)
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#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
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@ -97,7 +101,7 @@
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/* Wave Computing: "nanoMIPS" */
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#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
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#define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A)
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#define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_LEXT)
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/*
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* Strictly follow the architecture standard:
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|
|
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File diff suppressed because it is too large
Load Diff
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@ -1046,7 +1046,7 @@ enum {
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OPC_BC2NEZ = (0x0D << 21) | OPC_CP2,
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};
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#define MASK_LMI(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)) | (op & 0x1F))
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#define MASK_LMMI(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)) | (op & 0x1F))
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enum {
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OPC_PADDSH = (24 << 21) | (0x00) | OPC_CP2,
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@ -3421,7 +3421,8 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
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TCGv t0, t1, t2;
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int mem_idx = ctx->mem_idx;
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if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)) {
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if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F |
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INSN_LOONGSON3A)) {
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/*
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* Loongson CPU uses a load to zero register for prefetch.
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* We emulate it as a NOP. On other CPU we must perform the
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@ -5531,7 +5532,7 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
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TCGv_i64 t0, t1;
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TCGCond cond;
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opc = MASK_LMI(ctx->opcode);
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opc = MASK_LMMI(ctx->opcode);
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switch (opc) {
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case OPC_ADD_CP2:
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case OPC_SUB_CP2:
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@ -27161,7 +27162,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
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case OPC_MULTU_G_2F:
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case OPC_MOD_G_2F:
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case OPC_MODU_G_2F:
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check_insn(ctx, INSN_LOONGSON2F);
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check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
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gen_loongson_integer(ctx, op1, rd, rs, rt);
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break;
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case OPC_CLO:
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@ -27194,7 +27195,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
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case OPC_DDIVU_G_2F:
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case OPC_DMOD_G_2F:
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case OPC_DMODU_G_2F:
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check_insn(ctx, INSN_LOONGSON2F);
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check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
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gen_loongson_integer(ctx, op1, rd, rs, rt);
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break;
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#endif
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@ -29057,6 +29058,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
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break;
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||||
}
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||||
break;
|
||||
case OPC_MADDV_df:
|
||||
switch (df) {
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||||
case DF_BYTE:
|
||||
gen_helper_msa_maddv_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_maddv_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_maddv_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_maddv_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_MSUBV_df:
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_msubv_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_msubv_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_msubv_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_msubv_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_ASUB_S_df:
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
|
|
@ -29266,10 +29299,36 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
|
|||
}
|
||||
break;
|
||||
case OPC_SUBS_S_df:
|
||||
gen_helper_msa_subs_s_df(cpu_env, tdf, twd, tws, twt);
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_subs_s_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_subs_s_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_subs_s_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_subs_s_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_MULV_df:
|
||||
gen_helper_msa_mulv_df(cpu_env, tdf, twd, tws, twt);
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_mulv_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_mulv_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_mulv_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_mulv_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_SLD_df:
|
||||
gen_helper_msa_sld_df(cpu_env, tdf, twd, tws, twt);
|
||||
|
|
@ -29278,25 +29337,71 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
|
|||
gen_helper_msa_vshf_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_SUBV_df:
|
||||
gen_helper_msa_subv_df(cpu_env, tdf, twd, tws, twt);
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_subv_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_subv_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_subv_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_subv_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_SUBS_U_df:
|
||||
gen_helper_msa_subs_u_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_MADDV_df:
|
||||
gen_helper_msa_maddv_df(cpu_env, tdf, twd, tws, twt);
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_subs_u_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_subs_u_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_subs_u_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_subs_u_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_SPLAT_df:
|
||||
gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_SUBSUS_U_df:
|
||||
gen_helper_msa_subsus_u_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_MSUBV_df:
|
||||
gen_helper_msa_msubv_df(cpu_env, tdf, twd, tws, twt);
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_subsus_u_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_subsus_u_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_subsus_u_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_subsus_u_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_SUBSUU_S_df:
|
||||
gen_helper_msa_subsuu_s_df(cpu_env, tdf, twd, tws, twt);
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_subsuu_s_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_subsuu_s_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_subsuu_s_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_subsuu_s_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case OPC_DOTP_S_df:
|
||||
|
|
@ -29367,22 +29472,82 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
|
|||
}
|
||||
break;
|
||||
case OPC_DOTP_S_df:
|
||||
gen_helper_msa_dotp_s_df(cpu_env, tdf, twd, tws, twt);
|
||||
switch (df) {
|
||||
case DF_HALF:
|
||||
gen_helper_msa_dotp_s_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_dotp_s_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_dotp_s_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_DOTP_U_df:
|
||||
gen_helper_msa_dotp_u_df(cpu_env, tdf, twd, tws, twt);
|
||||
switch (df) {
|
||||
case DF_HALF:
|
||||
gen_helper_msa_dotp_u_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_dotp_u_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_dotp_u_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_DPADD_S_df:
|
||||
gen_helper_msa_dpadd_s_df(cpu_env, tdf, twd, tws, twt);
|
||||
switch (df) {
|
||||
case DF_HALF:
|
||||
gen_helper_msa_dpadd_s_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_dpadd_s_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_dpadd_s_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_DPADD_U_df:
|
||||
gen_helper_msa_dpadd_u_df(cpu_env, tdf, twd, tws, twt);
|
||||
switch (df) {
|
||||
case DF_HALF:
|
||||
gen_helper_msa_dpadd_u_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_dpadd_u_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_dpadd_u_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_DPSUB_S_df:
|
||||
gen_helper_msa_dpsub_s_df(cpu_env, tdf, twd, tws, twt);
|
||||
switch (df) {
|
||||
case DF_HALF:
|
||||
gen_helper_msa_dpsub_s_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_dpsub_s_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_dpsub_s_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_DPSUB_U_df:
|
||||
gen_helper_msa_dpsub_u_df(cpu_env, tdf, twd, tws, twt);
|
||||
switch (df) {
|
||||
case DF_HALF:
|
||||
gen_helper_msa_dpsub_u_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_dpsub_u_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_dpsub_u_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
|
@ -30641,7 +30806,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
|
|||
}
|
||||
break;
|
||||
case OPC_CP2:
|
||||
check_insn(ctx, INSN_LOONGSON2F);
|
||||
check_insn(ctx, ASE_LMMI);
|
||||
/* Note that these instructions use different fields. */
|
||||
gen_loongson_multimedia(ctx, sa, rd, rt);
|
||||
break;
|
||||
|
|
|
|||
Loading…
Reference in New Issue