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nvnet: Format the register list

This commit is contained in:
Matt Borgerson 2025-06-18 00:59:51 -07:00 committed by mborgerson
parent 144d3049a9
commit f4ab3ab830
2 changed files with 227 additions and 246 deletions
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200
hw/xbox/mcpx/nvnet/nvnet.c
View File

@ -82,47 +82,47 @@ struct RingDesc {
static const char *nvnet_get_reg_name(hwaddr addr) static const char *nvnet_get_reg_name(hwaddr addr)
{ {
switch (addr) { switch (addr) {
R(NvRegIrqStatus) R(NVNET_IRQ_STATUS)
R(NvRegIrqMask) R(NVNET_IRQ_MASK)
R(NvRegUnknownSetupReg6) R(NVNET_UNKNOWN_SETUP_REG6)
R(NvRegPollingInterval) R(NVNET_POLLING_INTERVAL)
R(NvRegMisc1) R(NVNET_MISC1)
R(NvRegTransmitterControl) R(NVNET_TRANSMITTER_CONTROL)
R(NvRegTransmitterStatus) R(NVNET_TRANSMITTER_STATUS)
R(NvRegPacketFilterFlags) R(NVNET_PACKET_FILTER)
R(NvRegOffloadConfig) R(NVNET_OFFLOAD)
R(NvRegReceiverControl) R(NVNET_RECEIVER_CONTROL)
R(NvRegReceiverStatus) R(NVNET_RECEIVER_STATUS)
R(NvRegRandomSeed) R(NVNET_RANDOM_SEED)
R(NvRegUnknownSetupReg1) R(NVNET_UNKNOWN_SETUP_REG1)
R(NvRegUnknownSetupReg2) R(NVNET_UNKNOWN_SETUP_REG2)
R(NvRegMacAddrA) R(NVNET_MAC_ADDR_A)
R(NvRegMacAddrB) R(NVNET_MAC_ADDR_B)
R(NvRegMulticastAddrA) R(NVNET_MULTICAST_ADDR_A)
R(NvRegMulticastAddrB) R(NVNET_MULTICAST_ADDR_B)
R(NvRegMulticastMaskA) R(NVNET_MULTICAST_MASK_A)
R(NvRegMulticastMaskB) R(NVNET_MULTICAST_MASK_B)
R(NvRegTxRingPhysAddr) R(NVNET_TX_RING_PHYS_ADDR)
R(NvRegRxRingPhysAddr) R(NVNET_RX_RING_PHYS_ADDR)
R(NvRegRingSizes) R(NVNET_RING_SIZE)
R(NvRegUnknownTransmitterReg) R(NVNET_UNKNOWN_TRANSMITTER_REG)
R(NvRegLinkSpeed) R(NVNET_LINKSPEED)
R(NvRegUnknownSetupReg5) R(NVNET_UNKNOWN_SETUP_REG5)
R(NvRegUnknownSetupReg3) R(NVNET_UNKNOWN_SETUP_REG3)
R(NvRegUnknownSetupReg8) R(NVNET_UNKNOWN_SETUP_REG8)
R(NvRegUnknownSetupReg7) R(NVNET_UNKNOWN_SETUP_REG7)
R(NvRegTxRxControl) R(NVNET_TX_RX_CONTROL)
R(NvRegMIIStatus) R(NVNET_MII_STATUS)
R(NvRegUnknownSetupReg4) R(NVNET_UNKNOWN_SETUP_REG4)
R(NvRegAdapterControl) R(NVNET_ADAPTER_CONTROL)
R(NvRegMIISpeed) R(NVNET_MII_SPEED)
R(NvRegMIIControl) R(NVNET_MII_CONTROL)
R(NvRegMIIData) R(NVNET_MII_DATA)
R(NvRegWakeUpFlags) R(NVNET_WAKEUPFLAGS)
R(NvRegPatternCRC) R(NVNET_PATTERN_CRC)
R(NvRegPatternMask) R(NVNET_PATTERN_MASK)
R(NvRegPowerCap) R(NVNET_POWERCAP)
R(NvRegPowerState) R(NVNET_POWERSTATE)
default: default:
return "Unknown"; return "Unknown";
} }
@ -152,7 +152,7 @@ static void nvnet_dump_ring_descriptors(NvNetState *s)
NVNET_DPRINTF("------------------------------------------------\n"); NVNET_DPRINTF("------------------------------------------------\n");
for (int i = 0; i < s->tx_ring_size; i++) { for (int i = 0; i < s->tx_ring_size; i++) {
dma_addr_t tx_ring_addr = nvnet_get_reg(s, NvRegTxRingPhysAddr, 4); dma_addr_t tx_ring_addr = nvnet_get_reg(s, NVNET_TX_RING_PHYS_ADDR, 4);
tx_ring_addr += i * sizeof(desc); tx_ring_addr += i * sizeof(desc);
pci_dma_read(d, tx_ring_addr, &desc, sizeof(desc)); pci_dma_read(d, tx_ring_addr, &desc, sizeof(desc));
NVNET_DPRINTF("TX: Dumping ring desc %d (%" HWADDR_PRIx "): ", NVNET_DPRINTF("TX: Dumping ring desc %d (%" HWADDR_PRIx "): ",
@ -164,7 +164,7 @@ static void nvnet_dump_ring_descriptors(NvNetState *s)
NVNET_DPRINTF("------------------------------------------------\n"); NVNET_DPRINTF("------------------------------------------------\n");
for (int i = 0; i < s->rx_ring_size; i++) { for (int i = 0; i < s->rx_ring_size; i++) {
dma_addr_t rx_ring_addr = nvnet_get_reg(s, NvRegRxRingPhysAddr, 4); dma_addr_t rx_ring_addr = nvnet_get_reg(s, NVNET_RX_RING_PHYS_ADDR, 4);
rx_ring_addr += i * sizeof(desc); rx_ring_addr += i * sizeof(desc);
pci_dma_read(d, rx_ring_addr, &desc, sizeof(desc)); pci_dma_read(d, rx_ring_addr, &desc, sizeof(desc));
NVNET_DPRINTF("RX: Dumping ring desc %d (%" HWADDR_PRIx "): ", NVNET_DPRINTF("RX: Dumping ring desc %d (%" HWADDR_PRIx "): ",
@ -228,8 +228,8 @@ static void nvnet_update_irq(NvNetState *s)
{ {
PCIDevice *d = PCI_DEVICE(s); PCIDevice *d = PCI_DEVICE(s);
uint32_t irq_mask = nvnet_get_reg(s, NvRegIrqMask, 4); uint32_t irq_mask = nvnet_get_reg(s, NVNET_IRQ_MASK, 4);
uint32_t irq_status = nvnet_get_reg(s, NvRegIrqStatus, 4); uint32_t irq_status = nvnet_get_reg(s, NVNET_IRQ_STATUS, 4);
if (irq_mask & irq_status) { if (irq_mask & irq_status) {
NVNET_DPRINTF("Asserting IRQ\n"); NVNET_DPRINTF("Asserting IRQ\n");
@ -253,14 +253,14 @@ static ssize_t nvnet_dma_packet_to_guest(NvNetState *s,
PCIDevice *d = PCI_DEVICE(s); PCIDevice *d = PCI_DEVICE(s);
bool did_receive = false; bool did_receive = false;
nvnet_set_reg(s, NvRegTxRxControl, nvnet_set_reg(s, NVNET_TX_RX_CONTROL,
nvnet_get_reg(s, NvRegTxRxControl, 4) & ~NVREG_TXRXCTL_IDLE, nvnet_get_reg(s, NVNET_TX_RX_CONTROL, 4) & ~NVNET_TX_RX_CONTROL_IDLE,
4); 4);
for (int i = 0; i < s->rx_ring_size; i++) { for (int i = 0; i < s->rx_ring_size; i++) {
struct RingDesc desc; struct RingDesc desc;
s->rx_ring_index %= s->rx_ring_size; s->rx_ring_index %= s->rx_ring_size;
dma_addr_t rx_ring_addr = nvnet_get_reg(s, NvRegRxRingPhysAddr, 4); dma_addr_t rx_ring_addr = nvnet_get_reg(s, NVNET_RX_RING_PHYS_ADDR, 4);
rx_ring_addr += s->rx_ring_index * sizeof(desc); rx_ring_addr += s->rx_ring_index * sizeof(desc);
pci_dma_read(d, rx_ring_addr, &desc, sizeof(desc)); pci_dma_read(d, rx_ring_addr, &desc, sizeof(desc));
@ -292,15 +292,15 @@ static ssize_t nvnet_dma_packet_to_guest(NvNetState *s,
/* Trigger interrupt */ /* Trigger interrupt */
NVNET_DPRINTF("Triggering interrupt\n"); NVNET_DPRINTF("Triggering interrupt\n");
uint32_t irq_status = nvnet_get_reg(s, NvRegIrqStatus, 4); uint32_t irq_status = nvnet_get_reg(s, NVNET_IRQ_STATUS, 4);
nvnet_set_reg(s, NvRegIrqStatus, irq_status | NVREG_IRQSTAT_BIT1, 4); nvnet_set_reg(s, NVNET_IRQ_STATUS, irq_status | NVNET_IRQ_STATUS_RX, 4);
nvnet_update_irq(s); nvnet_update_irq(s);
did_receive = true; did_receive = true;
break; break;
} }
nvnet_set_reg(s, NvRegTxRxControl, nvnet_set_reg(s, NVNET_TX_RX_CONTROL,
nvnet_get_reg(s, NvRegTxRxControl, 4) | NVREG_TXRXCTL_IDLE, nvnet_get_reg(s, NVNET_TX_RX_CONTROL, 4) | NVNET_TX_RX_CONTROL_IDLE,
4); 4);
if (did_receive) { if (did_receive) {
@ -316,15 +316,15 @@ static ssize_t nvnet_dma_packet_from_guest(NvNetState *s)
PCIDevice *d = PCI_DEVICE(s); PCIDevice *d = PCI_DEVICE(s);
bool packet_sent = false; bool packet_sent = false;
nvnet_set_reg(s, NvRegTxRxControl, nvnet_set_reg(s, NVNET_TX_RX_CONTROL,
nvnet_get_reg(s, NvRegTxRxControl, 4) & ~NVREG_TXRXCTL_IDLE, nvnet_get_reg(s, NVNET_TX_RX_CONTROL, 4) & ~NVNET_TX_RX_CONTROL_IDLE,
4); 4);
for (int i = 0; i < s->tx_ring_size; i++) { for (int i = 0; i < s->tx_ring_size; i++) {
/* Read ring descriptor */ /* Read ring descriptor */
struct RingDesc desc; struct RingDesc desc;
s->tx_ring_index %= s->tx_ring_size; s->tx_ring_index %= s->tx_ring_size;
dma_addr_t tx_ring_addr = nvnet_get_reg(s, NvRegTxRingPhysAddr, 4); dma_addr_t tx_ring_addr = nvnet_get_reg(s, NVNET_TX_RING_PHYS_ADDR, 4);
tx_ring_addr += s->tx_ring_index * sizeof(desc); tx_ring_addr += s->tx_ring_index * sizeof(desc);
pci_dma_read(d, tx_ring_addr, &desc, sizeof(desc)); pci_dma_read(d, tx_ring_addr, &desc, sizeof(desc));
@ -368,13 +368,13 @@ static ssize_t nvnet_dma_packet_from_guest(NvNetState *s)
if (packet_sent) { if (packet_sent) {
NVNET_DPRINTF("Triggering interrupt\n"); NVNET_DPRINTF("Triggering interrupt\n");
uint32_t irq_status = nvnet_get_reg(s, NvRegIrqStatus, 4); uint32_t irq_status = nvnet_get_reg(s, NVNET_IRQ_STATUS, 4);
nvnet_set_reg(s, NvRegIrqStatus, irq_status | NVREG_IRQSTAT_BIT4, 4); nvnet_set_reg(s, NVNET_IRQ_STATUS, irq_status | NVNET_IRQ_STATUS_TX, 4);
nvnet_update_irq(s); nvnet_update_irq(s);
} }
nvnet_set_reg(s, NvRegTxRxControl, nvnet_set_reg(s, NVNET_TX_RX_CONTROL,
nvnet_get_reg(s, NvRegTxRxControl, 4) | NVREG_TXRXCTL_IDLE, nvnet_get_reg(s, NVNET_TX_RX_CONTROL, 4) | NVNET_TX_RX_CONTROL_IDLE,
4); 4);
return 0; return 0;
@ -397,7 +397,7 @@ static bool receive_filter(NvNetState *s, const uint8_t *buf, int size)
return false; return false;
} }
uint32_t rctl = nvnet_get_reg(s, NvRegPacketFilterFlags, 4); uint32_t rctl = nvnet_get_reg(s, NVNET_PACKET_FILTER, 4);
/* Broadcast */ /* Broadcast */
if (is_broadcast_ether_addr(buf)) { if (is_broadcast_ether_addr(buf)) {
@ -406,20 +406,20 @@ static bool receive_filter(NvNetState *s, const uint8_t *buf, int size)
return true; return true;
} }
if (!(rctl & NVREG_PFF_MYADDR)) { if (!(rctl & NVNET_PACKET_FILTER_MYADDR)) {
/* FIXME: Confirm PFF_MYADDR filters mcast */ /* FIXME: Confirm PFF_MYADDR filters mcast */
return true; return true;
} }
/* Multicast */ /* Multicast */
uint32_t addr[2]; uint32_t addr[2];
addr[0] = cpu_to_le32(nvnet_get_reg(s, NvRegMulticastAddrA, 4)); addr[0] = cpu_to_le32(nvnet_get_reg(s, NVNET_MULTICAST_ADDR_A, 4));
addr[1] = cpu_to_le32(nvnet_get_reg(s, NvRegMulticastAddrB, 4)); addr[1] = cpu_to_le32(nvnet_get_reg(s, NVNET_MULTICAST_ADDR_B, 4));
if (!is_broadcast_ether_addr((uint8_t *)addr)) { if (!is_broadcast_ether_addr((uint8_t *)addr)) {
uint32_t dest_addr[2]; uint32_t dest_addr[2];
memcpy(dest_addr, buf, 6); memcpy(dest_addr, buf, 6);
dest_addr[0] &= cpu_to_le32(nvnet_get_reg(s, NvRegMulticastMaskA, 4)); dest_addr[0] &= cpu_to_le32(nvnet_get_reg(s, NVNET_MULTICAST_MASK_A, 4));
dest_addr[1] &= cpu_to_le32(nvnet_get_reg(s, NvRegMulticastMaskB, 4)); dest_addr[1] &= cpu_to_le32(nvnet_get_reg(s, NVNET_MULTICAST_MASK_B, 4));
if (!memcmp(dest_addr, addr, 6)) { if (!memcmp(dest_addr, addr, 6)) {
trace_nvnet_rx_filter_mcast_match(MAC_ARG(dest_addr)); trace_nvnet_rx_filter_mcast_match(MAC_ARG(dest_addr));
@ -430,8 +430,8 @@ static bool receive_filter(NvNetState *s, const uint8_t *buf, int size)
} }
/* Unicast */ /* Unicast */
addr[0] = cpu_to_le32(nvnet_get_reg(s, NvRegMacAddrA, 4)); addr[0] = cpu_to_le32(nvnet_get_reg(s, NVNET_MAC_ADDR_A, 4));
addr[1] = cpu_to_le32(nvnet_get_reg(s, NvRegMacAddrB, 4)); addr[1] = cpu_to_le32(nvnet_get_reg(s, NVNET_MAC_ADDR_B, 4));
if (!memcmp(buf, addr, 6)) { if (!memcmp(buf, addr, 6)) {
trace_nvnet_rx_filter_ucast_match(MAC_ARG(buf)); trace_nvnet_rx_filter_ucast_match(MAC_ARG(buf));
return true; return true;
@ -480,10 +480,10 @@ static ssize_t nvnet_receive(NetClientState *nc,
static void nvnet_mii_read(NvNetState *s) static void nvnet_mii_read(NvNetState *s)
{ {
uint32_t mii_ctl = nvnet_get_reg(s, NvRegMIIControl, 4); uint32_t mii_ctl = nvnet_get_reg(s, NVNET_MII_CONTROL, 4);
uint32_t mii_data = -1; uint32_t mii_data = -1;
uint32_t phy_addr = GET_MASK(mii_ctl, NVREG_MIICTL_PHYADDR); uint32_t phy_addr = GET_MASK(mii_ctl, NVNET_MII_CONTROL_PHYADDR);
uint32_t phy_reg = GET_MASK(mii_ctl, NVREG_MIICTL_PHYREG); uint32_t phy_reg = GET_MASK(mii_ctl, NVNET_MII_CONTROL_PHYREG);
if (phy_addr != 1) { if (phy_addr != 1) {
goto out; goto out;
@ -508,22 +508,22 @@ static void nvnet_mii_read(NvNetState *s)
} }
out: out:
mii_ctl &= ~NVREG_MIICTL_INUSE; mii_ctl &= ~NVNET_MII_CONTROL_INUSE;
nvnet_set_reg(s, NvRegMIIControl, mii_ctl, 4); nvnet_set_reg(s, NVNET_MII_CONTROL, mii_ctl, 4);
nvnet_set_reg(s, NvRegMIIData, mii_data, 4); nvnet_set_reg(s, NVNET_MII_DATA, mii_data, 4);
trace_nvnet_mii_read(phy_addr, phy_reg, nvnet_get_mii_reg_name(phy_reg), trace_nvnet_mii_read(phy_addr, phy_reg, nvnet_get_mii_reg_name(phy_reg),
mii_data); mii_data);
} }
static void nvnet_mii_write(NvNetState *s) static void nvnet_mii_write(NvNetState *s)
{ {
uint32_t mii_ctl = nvnet_get_reg(s, NvRegMIIControl, 4); uint32_t mii_ctl = nvnet_get_reg(s, NVNET_MII_CONTROL, 4);
uint32_t mii_data = nvnet_get_reg(s, NvRegMIIData, 4); uint32_t mii_data = nvnet_get_reg(s, NVNET_MII_DATA, 4);
uint32_t phy_addr = GET_MASK(mii_ctl, NVREG_MIICTL_PHYADDR); uint32_t phy_addr = GET_MASK(mii_ctl, NVNET_MII_CONTROL_PHYADDR);
uint32_t phy_reg = GET_MASK(mii_ctl, NVREG_MIICTL_PHYREG); uint32_t phy_reg = GET_MASK(mii_ctl, NVNET_MII_CONTROL_PHYREG);
mii_ctl &= ~NVREG_MIICTL_INUSE; mii_ctl &= ~NVNET_MII_CONTROL_INUSE;
nvnet_set_reg(s, NvRegMIIControl, mii_ctl, 4); nvnet_set_reg(s, NVNET_MII_CONTROL, mii_ctl, 4);
trace_nvnet_mii_write(phy_addr, phy_reg, nvnet_get_mii_reg_name(phy_reg), trace_nvnet_mii_write(phy_addr, phy_reg, nvnet_get_mii_reg_name(phy_reg),
mii_data); mii_data);
} }
@ -534,7 +534,7 @@ static uint64_t nvnet_mmio_read(void *opaque, hwaddr addr, unsigned int size)
uint64_t retval; uint64_t retval;
switch (addr) { switch (addr) {
case NvRegMIIStatus: case NVNET_MII_STATUS:
retval = 0; retval = 0;
break; break;
@ -556,63 +556,63 @@ static void nvnet_mmio_write(void *opaque, hwaddr addr,
trace_nvnet_reg_write(addr, nvnet_get_reg_name(addr & ~3), size, val); trace_nvnet_reg_write(addr, nvnet_get_reg_name(addr & ~3), size, val);
switch (addr) { switch (addr) {
case NvRegRingSizes: case NVNET_RING_SIZE:
nvnet_set_reg(s, addr, val, size); nvnet_set_reg(s, addr, val, size);
s->rx_ring_size = ((val >> NVREG_RINGSZ_RXSHIFT) & 0xffff) + 1; s->rx_ring_size = ((val >> NVNET_RING_SIZE_RXSHIFT) & 0xffff) + 1;
s->tx_ring_size = ((val >> NVREG_RINGSZ_TXSHIFT) & 0xffff) + 1; s->tx_ring_size = ((val >> NVNET_RING_SIZE_TXSHIFT) & 0xffff) + 1;
break; break;
case NvRegMIIControl: case NVNET_MII_CONTROL:
assert(size == 4); assert(size == 4);
nvnet_set_reg(s, addr, val, size); nvnet_set_reg(s, addr, val, size);
if (val & NVREG_MIICTL_WRITE) { if (val & NVNET_MII_CONTROL_WRITE) {
nvnet_mii_write(s); nvnet_mii_write(s);
} else { } else {
nvnet_mii_read(s); nvnet_mii_read(s);
} }
break; break;
case NvRegTxRxControl: case NVNET_TX_RX_CONTROL:
if (val == NVREG_TXRXCTL_KICK) { if (val == NVNET_TX_RX_CONTROL_KICK) {
NVNET_DPRINTF("NvRegTxRxControl = NVREG_TXRXCTL_KICK!\n"); NVNET_DPRINTF("NVNET_TX_RX_CONTROL = NVNET_TX_RX_CONTROL_KICK!\n");
nvnet_dump_ring_descriptors(s); nvnet_dump_ring_descriptors(s);
nvnet_dma_packet_from_guest(s); nvnet_dma_packet_from_guest(s);
} }
if (val & NVREG_TXRXCTL_BIT2) { if (val & NVNET_TX_RX_CONTROL_BIT2) {
nvnet_set_reg(s, NvRegTxRxControl, NVREG_TXRXCTL_IDLE, 4); nvnet_set_reg(s, NVNET_TX_RX_CONTROL, NVNET_TX_RX_CONTROL_IDLE, 4);
break; break;
} }
if (val & NVREG_TXRXCTL_RESET) { if (val & NVNET_TX_RX_CONTROL_RESET) {
s->tx_ring_index = 0; s->tx_ring_index = 0;
s->rx_ring_index = 0; s->rx_ring_index = 0;
s->tx_dma_buf_offset = 0; s->tx_dma_buf_offset = 0;
} }
if (val & NVREG_TXRXCTL_BIT1) { if (val & NVNET_TX_RX_CONTROL_BIT1) {
// FIXME // FIXME
nvnet_set_reg(s, NvRegIrqStatus, 0, 4); nvnet_set_reg(s, NVNET_IRQ_STATUS, 0, 4);
break; break;
} else if (val == 0) { } else if (val == 0) {
temp = nvnet_get_reg(s, NvRegUnknownSetupReg3, 4); temp = nvnet_get_reg(s, NVNET_UNKNOWN_SETUP_REG3, 4);
if (temp == NVREG_UNKSETUP3_VAL1) { if (temp == NVNET_UNKNOWN_SETUP_REG3_VAL1) {
/* forcedeth waits for this bit to be set... */ /* forcedeth waits for this bit to be set... */
nvnet_set_reg(s, NvRegUnknownSetupReg5, nvnet_set_reg(s, NVNET_UNKNOWN_SETUP_REG5,
NVREG_UNKSETUP5_BIT31, 4); NVNET_UNKNOWN_SETUP_REG5_BIT31, 4);
break; break;
} }
} }
nvnet_set_reg(s, NvRegTxRxControl, val, size); nvnet_set_reg(s, NVNET_TX_RX_CONTROL, val, size);
break; break;
case NvRegIrqMask: case NVNET_IRQ_MASK:
nvnet_set_reg(s, addr, val, size); nvnet_set_reg(s, addr, val, size);
nvnet_update_irq(s); nvnet_update_irq(s);
break; break;
case NvRegIrqStatus: case NVNET_IRQ_STATUS:
nvnet_set_reg(s, addr, nvnet_get_reg(s, addr, size) & ~val, size); nvnet_set_reg(s, addr, nvnet_get_reg(s, addr, size) & ~val, size);
nvnet_update_irq(s); nvnet_update_irq(s);
break; break;

273
hw/xbox/mcpx/nvnet/nvnet_regs.h
View File

@ -22,8 +22,8 @@
* Most definitions are based on forcedeth.c, taken from cromwell project. * Most definitions are based on forcedeth.c, taken from cromwell project.
* Original forcedeth.c license follows: * Original forcedeth.c license follows:
* *
* -- * --
* forcedeth.c -- Etherboot device driver for the NVIDIA nForce * forcedeth.c -- Etherboot device driver for the NVIDIA nForce
* media access controllers. * media access controllers.
* *
* Note: This driver is based on the Linux driver that was based on * Note: This driver is based on the Linux driver that was based on
@ -53,160 +53,141 @@
* *
* (C) 2003 Manfred Spraul * (C) 2003 Manfred Spraul
* See Linux Driver for full information * See Linux Driver for full information
* *
* Linux Driver Version 0.22, 19 Jan 2004 * Linux Driver Version 0.22, 19 Jan 2004
* *
* *
* REVISION HISTORY: * REVISION HISTORY:
* ================ * ================
* v1.0 01-31-2004 timlegge Initial port of Linux driver * v1.0 01-31-2004 timlegge Initial port of Linux driver
* v1.1 02-03-2004 timlegge Large Clean up, first release * v1.1 02-03-2004 timlegge Large Clean up, first release
* *
* Indent Options: indent -kr -i8 * Indent Options: indent -kr -i8
***************************************************************************/ ***************************************************************************/
#ifndef HW_NVNET_REGS_H #ifndef HW_NVNET_REGS_H
#define HW_NVNET_REGS_H #define HW_NVNET_REGS_H
// clang-format on // clang-format off
#define DEV_NEED_LASTPACKET1 0x0001 #define NVNET_IRQ_STATUS 0x000
#define DEV_IRQMASK_1 0x0002 # define NVNET_IRQ_STATUS_RX 0x00000002
#define DEV_IRQMASK_2 0x0004 # define NVNET_IRQ_STATUS_RX_NOBUF 0x00000004
#define DEV_NEED_TIMERIRQ 0x0008 # define NVNET_IRQ_STATUS_TX_ERR 0x00000008
# define NVNET_IRQ_STATUS_TX 0x00000010
enum { # define NVNET_IRQ_STATUS_TIMER 0x00000020
NvRegIrqStatus = 0x000, # define NVNET_IRQ_STATUS_MIIEVENT 0x00000040
# define NVREG_IRQSTAT_BIT1 0x002 #define NVNET_IRQ_MASK 0x004
# define NVREG_IRQSTAT_BIT4 0x010 #define NVNET_UNKNOWN_SETUP_REG6 0x008
# define NVREG_IRQSTAT_MIIEVENT 0x040 # define NVNET_UNKNOWN_SETUP_REG6_VAL 3
# define NVREG_IRQSTAT_MASK 0x1ff
NvRegIrqMask = 0x004,
# define NVREG_IRQ_RX 0x0002
# define NVREG_IRQ_RX_NOBUF 0x0004
# define NVREG_IRQ_TX_ERR 0x0008
# define NVREG_IRQ_TX2 0x0010
# define NVREG_IRQ_TIMER 0x0020
# define NVREG_IRQ_LINK 0x0040
# define NVREG_IRQ_TX1 0x0100
# define NVREG_IRQMASK_WANTED_1 0x005f
# define NVREG_IRQMASK_WANTED_2 0x0147
# define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX | NVREG_IRQ_RX_NOBUF | \
NVREG_IRQ_TX_ERR | NVREG_IRQ_TX2 | NVREG_IRQ_TIMER | NVREG_IRQ_LINK | \
NVREG_IRQ_TX1))
NvRegUnknownSetupReg6 = 0x008,
# define NVREG_UNKSETUP6_VAL 3
/* /*
* NVREG_POLL_DEFAULT is the interval length of the timer source on the nic * NVNET_POLLING_INTERVAL_DEFAULT is the interval length of the timer source on the nic
* NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms * NVNET_POLLING_INTERVAL_DEFAULT=97 would result in an interval length of 1 ms
*/ */
NvRegPollingInterval = 0x00c, #define NVNET_POLLING_INTERVAL 0x00C
# define NVREG_POLL_DEFAULT 970 # define NVNET_POLLING_INTERVAL_DEFAULT 970
NvRegMisc1 = 0x080, #define NVNET_MISC1 0x080
# define NVREG_MISC1_HD 0x02 # define NVNET_MISC1_HD 0x00000002
# define NVREG_MISC1_FORCE 0x3b0f3c # define NVNET_MISC1_FORCE 0x003B0F3C
NvRegTransmitterControl = 0x084, #define NVNET_TRANSMITTER_CONTROL 0x084
# define NVREG_XMITCTL_START 0x01 # define NVNET_TRANSMITTER_CONTROL_START 0x00000001
NvRegTransmitterStatus = 0x088, #define NVNET_TRANSMITTER_STATUS 0x088
# define NVREG_XMITSTAT_BUSY 0x01 # define NVNET_TRANSMITTER_STATUS_BUSY 0x00000001
NvRegPacketFilterFlags = 0x8c, #define NVNET_PACKET_FILTER 0x08C
# define NVREG_PFF_ALWAYS 0x7F0008 # define NVNET_PACKET_FILTER_ALWAYS 0x007F0008
# define NVREG_PFF_PROMISC 0x80 # define NVNET_PACKET_FILTER_PROMISC 0x00000080
# define NVREG_PFF_MYADDR 0x20 # define NVNET_PACKET_FILTER_MYADDR 0x00000020
NvRegOffloadConfig = 0x90, #define NVNET_OFFLOAD 0x090
# define NVREG_OFFLOAD_HOMEPHY 0x601 # define NVNET_OFFLOAD_HOMEPHY 0x00000601
# define NVREG_OFFLOAD_NORMAL 0x5ee # define NVNET_OFFLOAD_NORMAL 0x000005EE
NvRegReceiverControl = 0x094, #define NVNET_RECEIVER_CONTROL 0x094
# define NVREG_RCVCTL_START 0x01 # define NVNET_RECEIVER_CONTROL_START 0x00000001
NvRegReceiverStatus = 0x98, #define NVNET_RECEIVER_STATUS 0x098
# define NVREG_RCVSTAT_BUSY 0x01 # define NVNET_RECEIVER_STATUS_BUSY 0x00000001
NvRegRandomSeed = 0x9c, #define NVNET_RANDOM_SEED 0x09C
# define NVREG_RNDSEED_MASK 0x00ff # define NVNET_RANDOM_SEED_MASK 0x000000FF
# define NVREG_RNDSEED_FORCE 0x7f00 # define NVNET_RANDOM_SEED_FORCE 0x00007F00
NvRegUnknownSetupReg1 = 0xA0, #define NVNET_UNKNOWN_SETUP_REG1 0x0A0
# define NVREG_UNKSETUP1_VAL 0x16070f # define NVNET_UNKNOWN_SETUP_REG1_VAL 0x0016070F
NvRegUnknownSetupReg2 = 0xA4, #define NVNET_UNKNOWN_SETUP_REG2 0x0A4
# define NVREG_UNKSETUP2_VAL 0x16 # define NVNET_UNKNOWN_SETUP_REG2_VAL 0x00000016
NvRegMacAddrA = 0xA8, #define NVNET_MAC_ADDR_A 0x0A8
NvRegMacAddrB = 0xAC, #define NVNET_MAC_ADDR_B 0x0AC
NvRegMulticastAddrA = 0xB0, #define NVNET_MULTICAST_ADDR_A 0x0B0
# define NVREG_MCASTADDRA_FORCE 0x01 # define NVNET_MULTICAST_ADDR_A_FORCE 0x00000001
NvRegMulticastAddrB = 0xB4, #define NVNET_MULTICAST_ADDR_B 0x0B4
NvRegMulticastMaskA = 0xB8, #define NVNET_MULTICAST_MASK_A 0x0B8
NvRegMulticastMaskB = 0xBC, #define NVNET_MULTICAST_MASK_B 0x0BC
NvRegTxRingPhysAddr = 0x100, #define NVNET_TX_RING_PHYS_ADDR 0x100
NvRegRxRingPhysAddr = 0x104, #define NVNET_RX_RING_PHYS_ADDR 0x104
NvRegRingSizes = 0x108, #define NVNET_RING_SIZE 0x108
# define NVREG_RINGSZ_TXSHIFT 0 # define NVNET_RING_SIZE_TXSHIFT 0
# define NVREG_RINGSZ_RXSHIFT 16 # define NVNET_RING_SIZE_RXSHIFT 16
NvRegUnknownTransmitterReg = 0x10c, #define NVNET_UNKNOWN_TRANSMITTER_REG 0x10C
NvRegLinkSpeed = 0x110, #define NVNET_LINKSPEED 0x110
# define NVREG_LINKSPEED_FORCE 0x10000 # define NVNET_LINKSPEED_FORCE 0x00010000
# define NVREG_LINKSPEED_10 10 # define NVNET_LINKSPEED_10 10
# define NVREG_LINKSPEED_100 100 # define NVNET_LINKSPEED_100 100
# define NVREG_LINKSPEED_1000 1000 # define NVNET_LINKSPEED_1000 1000
NvRegUnknownSetupReg5 = 0x130, #define NVNET_UNKNOWN_SETUP_REG5 0x130
# define NVREG_UNKSETUP5_BIT31 (1 << 31) # define NVNET_UNKNOWN_SETUP_REG5_BIT31 (1 << 31)
NvRegUnknownSetupReg3 = 0x134, #define NVNET_UNKNOWN_SETUP_REG3 0x134
# define NVREG_UNKSETUP3_VAL1 0x200010 # define NVNET_UNKNOWN_SETUP_REG3_VAL1 0x00200010
NvRegUnknownSetupReg8 = 0x13C, #define NVNET_UNKNOWN_SETUP_REG8 0x13C
# define NVREG_UNKSETUP8_VAL1 0x300010 # define NVNET_UNKNOWN_SETUP_REG8_VAL1 0x00300010
NvRegUnknownSetupReg7 = 0x140, #define NVNET_UNKNOWN_SETUP_REG7 0x140
# define NVREG_UNKSETUP7_VAL 0x300010 # define NVNET_UNKNOWN_SETUP_REG7_VAL 0x00300010
NvRegTxRxControl = 0x144, #define NVNET_TX_RX_CONTROL 0x144
# define NVREG_TXRXCTL_KICK 0x0001 # define NVNET_TX_RX_CONTROL_KICK 0x00000001
# define NVREG_TXRXCTL_BIT1 0x0002 # define NVNET_TX_RX_CONTROL_BIT1 0x00000002
# define NVREG_TXRXCTL_BIT2 0x0004 # define NVNET_TX_RX_CONTROL_BIT2 0x00000004
# define NVREG_TXRXCTL_IDLE 0x0008 # define NVNET_TX_RX_CONTROL_IDLE 0x00000008
# define NVREG_TXRXCTL_RESET 0x0010 # define NVNET_TX_RX_CONTROL_RESET 0x00000010
NvRegMIIStatus = 0x180, #define NVNET_MII_STATUS 0x180
# define NVREG_MIISTAT_ERROR 0x0001 # define NVNET_MII_STATUS_ERROR 0x00000001
# define NVREG_MIISTAT_LINKCHANGE 0x0008 # define NVNET_MII_STATUS_LINKCHANGE 0x00000008
# define NVREG_MIISTAT_MASK 0x000f #define NVNET_UNKNOWN_SETUP_REG4 0x184
# define NVREG_MIISTAT_MASK2 0x000f # define NVNET_UNKNOWN_SETUP_REG4_VAL 8
NvRegUnknownSetupReg4 = 0x184, #define NVNET_ADAPTER_CONTROL 0x188
# define NVREG_UNKSETUP4_VAL 8 # define NVNET_ADAPTER_CONTROL_START 0x00000002
NvRegAdapterControl = 0x188, # define NVNET_ADAPTER_CONTROL_LINKUP 0x00000004
# define NVREG_ADAPTCTL_START 0x02 # define NVNET_ADAPTER_CONTROL_PHYVALID 0x00004000
# define NVREG_ADAPTCTL_LINKUP 0x04 # define NVNET_ADAPTER_CONTROL_RUNNING 0x00100000
# define NVREG_ADAPTCTL_PHYVALID 0x4000 # define NVNET_ADAPTER_CONTROL_PHYSHIFT 24
# define NVREG_ADAPTCTL_RUNNING 0x100000 #define NVNET_MII_SPEED 0x18C
# define NVREG_ADAPTCTL_PHYSHIFT 24 # define NVNET_MII_SPEED_BIT8 (1 << 8)
NvRegMIISpeed = 0x18c, # define NVNET_MII_SPEED_DELAY 5
# define NVREG_MIISPEED_BIT8 (1 << 8) #define NVNET_MII_CONTROL 0x190
# define NVREG_MIIDELAY 5 # define NVNET_MII_CONTROL_INUSE 0x00008000
NvRegMIIControl = 0x190, # define NVNET_MII_CONTROL_WRITE 0x00000400
# define NVREG_MIICTL_INUSE 0x8000 # define NVNET_MII_CONTROL_PHYADDR 0x000003E0
# define NVREG_MIICTL_WRITE 0x0400 # define NVNET_MII_CONTROL_PHYREG 0x0000001F
# define NVREG_MIICTL_PHYADDR 0x03e0 #define NVNET_MII_DATA 0x194
# define NVREG_MIICTL_PHYREG 0x001f #define NVNET_WAKEUPFLAGS 0x200
NvRegMIIData = 0x194, # define NVNET_WAKEUPFLAGS_VAL 0x00007770
NvRegWakeUpFlags = 0x200, # define NVNET_WAKEUPFLAGS_BUSYSHIFT 24
# define NVREG_WAKEUPFLAGS_VAL 0x7770 # define NVNET_WAKEUPFLAGS_ENABLESHIFT 16
# define NVREG_WAKEUPFLAGS_BUSYSHIFT 24 # define NVNET_WAKEUPFLAGS_D3SHIFT 12
# define NVREG_WAKEUPFLAGS_ENABLESHIFT 16 # define NVNET_WAKEUPFLAGS_D2SHIFT 8
# define NVREG_WAKEUPFLAGS_D3SHIFT 12 # define NVNET_WAKEUPFLAGS_D1SHIFT 4
# define NVREG_WAKEUPFLAGS_D2SHIFT 8 # define NVNET_WAKEUPFLAGS_D0SHIFT 0
# define NVREG_WAKEUPFLAGS_D1SHIFT 4 # define NVNET_WAKEUPFLAGS_ACCEPT_MAGPAT 0x00000001
# define NVREG_WAKEUPFLAGS_D0SHIFT 0 # define NVNET_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x00000002
# define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01 # define NVNET_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x00000004
# define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02 #define NVNET_PATTERN_CRC 0x204
# define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04 #define NVNET_PATTERN_MASK 0x208
NvRegPatternCRC = 0x204, #define NVNET_POWERCAP 0x268
NvRegPatternMask = 0x208, # define NVNET_POWERCAP_D3SUPP (1 << 30)
NvRegPowerCap = 0x268, # define NVNET_POWERCAP_D2SUPP (1 << 26)
# define NVREG_POWERCAP_D3SUPP (1 << 30) # define NVNET_POWERCAP_D1SUPP (1 << 25)
# define NVREG_POWERCAP_D2SUPP (1 << 26) #define NVNET_POWERSTATE 0x26C
# define NVREG_POWERCAP_D1SUPP (1 << 25) # define NVNET_POWERSTATE_POWEREDUP 0x00008000
NvRegPowerState = 0x26c, # define NVNET_POWERSTATE_VALID 0x00000100
# define NVREG_POWERSTATE_POWEREDUP 0x8000 # define NVNET_POWERSTATE_MASK 0x00000003
# define NVREG_POWERSTATE_VALID 0x0100 # define NVNET_POWERSTATE_D0 0x00000000
# define NVREG_POWERSTATE_MASK 0x0003 # define NVNET_POWERSTATE_D1 0x00000001
# define NVREG_POWERSTATE_D0 0x0000 # define NVNET_POWERSTATE_D2 0x00000002
# define NVREG_POWERSTATE_D1 0x0001 # define NVNET_POWERSTATE_D3 0x00000003
# define NVREG_POWERSTATE_D2 0x0002
# define NVREG_POWERSTATE_D3 0x0003
};
#define NV_TX_LASTPACKET (1 << 0) #define NV_TX_LASTPACKET (1 << 0)
#define NV_TX_RETRYERROR (1 << 3) #define NV_TX_RETRYERROR (1 << 3)
@ -272,11 +253,11 @@ enum {
#define POLL_WAIT (1 + HZ / 100) #define POLL_WAIT (1 + HZ / 100)
/* Link partner ability register. */ /* Link partner ability register. */
#define LPA_SLCT 0x001f /* Same as advertise selector */ #define LPA_SLCT 0x001F /* Same as advertise selector */
#define LPA_RESV 0x1c00 /* Unused... */ #define LPA_RESV 0x1C00 /* Unused... */
#define LPA_RFAULT 0x2000 /* Link partner faulted */ #define LPA_RFAULT 0x2000 /* Link partner faulted */
#define LPA_NPAGE 0x8000 /* Next page bit */ #define LPA_NPAGE 0x8000 /* Next page bit */
// clang-format off // clang-format on
#endif /* HW_NVNET_REGS_H */ #endif /* HW_NVNET_REGS_H */