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riscv: sifive_u: Set the minimum number of cpus to 2 

It is not useful if we only have one management CPU.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
[Palmer: Set default CPUs to 2]
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Bin Meng 2019-09-06 09:20:05 -07:00 committed by Palmer Dabbelt
parent e8c56787cd
commit f3d47d5804
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GPG Key ID: EF4CA1502CCBAB41
2 changed files with 6 additions and 1 deletions
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5
hw/riscv/sifive_u.c
View File

@ -10,7 +10,8 @@
* 1) CLINT (Core Level Interruptor) * 1) CLINT (Core Level Interruptor)
* 2) PLIC (Platform Level Interrupt Controller) * 2) PLIC (Platform Level Interrupt Controller)
* *
* This board currently uses a hardcoded devicetree that indicates one hart. * This board currently generates devicetree dynamically that indicates at least
* two harts.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
@ -433,6 +434,8 @@ static void riscv_sifive_u_machine_init(MachineClass *mc)
* management CPU. * management CPU.
*/ */
mc->max_cpus = 4; mc->max_cpus = 4;
mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
mc->default_cpus = mc->min_cpus;
} }
DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)

2
include/hw/riscv/sifive_u.h
View File

@ -69,6 +69,8 @@ enum {
SIFIVE_U_GEM_CLOCK_FREQ = 125000000 SIFIVE_U_GEM_CLOCK_FREQ = 125000000
}; };
#define SIFIVE_U_MANAGEMENT_CPU_COUNT 1
#define SIFIVE_U_PLIC_HART_CONFIG "MS" #define SIFIVE_U_PLIC_HART_CONFIG "MS"
#define SIFIVE_U_PLIC_NUM_SOURCES 54 #define SIFIVE_U_PLIC_NUM_SOURCES 54
#define SIFIVE_U_PLIC_NUM_PRIORITIES 7 #define SIFIVE_U_PLIC_NUM_PRIORITIES 7