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target/i386: Fix carry flag for BLSI 

target/i386: Fix tss access size in switch_tss_ra
 linux-user: Handle short reads in mmap_h_gt_g
 bsd-user: Handle short reads in mmap_h_gt_g
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Merge tag 'pull-misc-20240821' of https://gitlab.com/rth7680/qemu into staging

target/i386: Fix carry flag for BLSI
target/i386: Fix tss access size in switch_tss_ra
linux-user: Handle short reads in mmap_h_gt_g
bsd-user: Handle short reads in mmap_h_gt_g

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# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
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# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]

* tag 'pull-misc-20240821' of https://gitlab.com/rth7680/qemu:
  target/i386: Fix tss access size in switch_tss_ra
  target/i386: Fix carry flag for BLSI
  target/i386: Split out gen_prepare_val_nz
  bsd-user: Handle short reads in mmap_h_gt_g
  linux-user: Handle short reads in mmap_h_gt_g

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-08-21 12:26:24 +10:00
parent 4220ebde10 ded1db48c9
commit f36538b86b
10 changed files with 163 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
bsd-user/mmap.c
View File

@ -128,6 +128,40 @@ error:
return ret;
}
/*
* Perform a pread on behalf of target_mmap. We can reach EOF, we can be
* interrupted by signals, and in general there's no good error return path.
* If @zero, zero the rest of the block at EOF.
* Return true on success.
*/
static bool mmap_pread(int fd, void *p, size_t len, off_t offset, bool zero)
{
while (1) {
ssize_t r = pread(fd, p, len, offset);
if (likely(r == len)) {
/* Complete */
return true;
}
if (r == 0) {
/* EOF */
if (zero) {
memset(p, 0, len);
}
return true;
}
if (r > 0) {
/* Short read */
p += r;
len -= r;
offset += r;
} else if (errno != EINTR) {
/* Error */
return false;
}
}
}
/*
* map an incomplete host page
*
@ -190,7 +224,7 @@ static int mmap_frag(abi_ulong real_start,
mprotect(host_start, qemu_host_page_size, prot1 | PROT_WRITE);
/* read the corresponding file data */
if (pread(fd, g2h_untagged(start), end - start, offset) == -1) {
if (!mmap_pread(fd, g2h_untagged(start), end - start, offset, true)) {
return -1;
}
@ -565,7 +599,7 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int prot,
-1, 0);
if (retaddr == -1)
goto fail;
if (pread(fd, g2h_untagged(start), len, offset) == -1) {
if (!mmap_pread(fd, g2h_untagged(start), len, offset, false)) {
goto fail;
}
if (!(prot & PROT_WRITE)) {

44
linux-user/mmap.c
View File

@ -283,6 +283,40 @@ static int do_munmap(void *addr, size_t len)
return munmap(addr, len);
}
/*
* Perform a pread on behalf of target_mmap. We can reach EOF, we can be
* interrupted by signals, and in general there's no good error return path.
* If @zero, zero the rest of the block at EOF.
* Return true on success.
*/
static bool mmap_pread(int fd, void *p, size_t len, off_t offset, bool zero)
{
while (1) {
ssize_t r = pread(fd, p, len, offset);
if (likely(r == len)) {
/* Complete */
return true;
}
if (r == 0) {
/* EOF */
if (zero) {
memset(p, 0, len);
}
return true;
}
if (r > 0) {
/* Short read */
p += r;
len -= r;
offset += r;
} else if (errno != EINTR) {
/* Error */
return false;
}
}
}
/*
* Map an incomplete host page.
*
@ -357,10 +391,9 @@ static bool mmap_frag(abi_ulong real_start, abi_ulong start, abi_ulong last,
/* Read or zero the new guest pages. */
if (flags & MAP_ANONYMOUS) {
memset(g2h_untagged(start), 0, last - start + 1);
} else {
if (pread(fd, g2h_untagged(start), last - start + 1, offset) == -1) {
return false;
}
} else if (!mmap_pread(fd, g2h_untagged(start), last - start + 1,
offset, true)) {
return false;
}
/* Put final protection */
@ -853,8 +886,7 @@ static abi_long mmap_h_gt_g(abi_ulong start, abi_ulong len,
}
if (misaligned_offset) {
/* TODO: The read could be short. */
if (pread(fd, p, host_len, offset + real_start - start) != host_len) {
if (!mmap_pread(fd, p, host_len, offset + real_start - start, false)) {
do_munmap(p, host_len);
return -1;
}

5
target/i386/cpu.h
View File

@ -1339,6 +1339,11 @@ typedef enum {
CC_OP_BMILGL,
CC_OP_BMILGQ,
CC_OP_BLSIB, /* Z,S via CC_DST, C = SRC!=0; O=0; P,A undefined */
CC_OP_BLSIW,
CC_OP_BLSIL,
CC_OP_BLSIQ,
/*
* Note that only CC_OP_POPCNT (i.e. the one with MO_TL size)
* is used or implemented, because the translation needs

18
target/i386/tcg/cc_helper.c
View File

@ -186,6 +186,13 @@ target_ulong helper_cc_compute_all(target_ulong dst, target_ulong src1,
case CC_OP_BMILGL:
return compute_all_bmilgl(dst, src1);
case CC_OP_BLSIB:
return compute_all_blsib(dst, src1);
case CC_OP_BLSIW:
return compute_all_blsiw(dst, src1);
case CC_OP_BLSIL:
return compute_all_blsil(dst, src1);
case CC_OP_ADCX:
return compute_all_adcx(dst, src1, src2);
case CC_OP_ADOX:
@ -216,6 +223,8 @@ target_ulong helper_cc_compute_all(target_ulong dst, target_ulong src1,
return compute_all_sarq(dst, src1);
case CC_OP_BMILGQ:
return compute_all_bmilgq(dst, src1);
case CC_OP_BLSIQ:
return compute_all_blsiq(dst, src1);
#endif
}
}
@ -308,6 +317,13 @@ target_ulong helper_cc_compute_c(target_ulong dst, target_ulong src1,
case CC_OP_BMILGL:
return compute_c_bmilgl(dst, src1);
case CC_OP_BLSIB:
return compute_c_blsib(dst, src1);
case CC_OP_BLSIW:
return compute_c_blsiw(dst, src1);
case CC_OP_BLSIL:
return compute_c_blsil(dst, src1);
#ifdef TARGET_X86_64
case CC_OP_ADDQ:
return compute_c_addq(dst, src1);
@ -321,6 +337,8 @@ target_ulong helper_cc_compute_c(target_ulong dst, target_ulong src1,
return compute_c_shlq(dst, src1);
case CC_OP_BMILGQ:
return compute_c_bmilgq(dst, src1);
case CC_OP_BLSIQ:
return compute_c_blsiq(dst, src1);
#endif
}
}

18
target/i386/tcg/cc_helper_template.h.inc
View File

@ -235,6 +235,24 @@ static int glue(compute_c_bmilg, SUFFIX)(DATA_TYPE dst, DATA_TYPE src1)
return src1 == 0;
}
static int glue(compute_all_blsi, SUFFIX)(DATA_TYPE dst, DATA_TYPE src1)
{
int cf, pf, af, zf, sf, of;
cf = (src1 != 0);
pf = 0; /* undefined */
af = 0; /* undefined */
zf = (dst == 0) * CC_Z;
sf = lshift(dst, 8 - DATA_BITS) & CC_S;
of = 0;
return cf | pf | af | zf | sf | of;
}
static int glue(compute_c_blsi, SUFFIX)(DATA_TYPE dst, DATA_TYPE src1)
{
return src1 != 0;
}
#undef DATA_BITS
#undef SIGN_MASK
#undef DATA_TYPE

2
target/i386/tcg/emit.c.inc
View File

@ -1304,7 +1304,7 @@ static void gen_BLSI(DisasContext *s, X86DecodedInsn *decode)
/* input in T1, which is ready for prepare_update2_cc */
tcg_gen_neg_tl(s->T0, s->T1);
tcg_gen_and_tl(s->T0, s->T0, s->T1);
prepare_update2_cc(decode, s, CC_OP_BMILGB + ot);
prepare_update2_cc(decode, s, CC_OP_BLSIB + ot);
}
static void gen_BLSMSK(DisasContext *s, X86DecodedInsn *decode)

5
target/i386/tcg/seg_helper.c
View File

@ -378,7 +378,7 @@ static int switch_tss_ra(CPUX86State *env, int tss_selector,
/* X86Access avoids memory exceptions during the task switch */
mmu_index = cpu_mmu_index_kernel(env);
access_prepare_mmu(&old, env, env->tr.base, old_tss_limit_max,
access_prepare_mmu(&old, env, env->tr.base, old_tss_limit_max + 1,
MMU_DATA_STORE, mmu_index, retaddr);
if (source == SWITCH_TSS_CALL) {
@ -386,7 +386,8 @@ static int switch_tss_ra(CPUX86State *env, int tss_selector,
probe_access(env, tss_base, 2, MMU_DATA_STORE,
mmu_index, retaddr);
}
access_prepare_mmu(&new, env, tss_base, tss_limit,
/* While true tss_limit may be larger, we don't access the iopb here. */
access_prepare_mmu(&new, env, tss_base, tss_limit_max + 1,
MMU_DATA_LOAD, mmu_index, retaddr);
/* save the current state in the old TSS */

27
target/i386/tcg/translate.c
View File

@ -304,6 +304,7 @@ static const uint8_t cc_op_live[CC_OP_NB] = {
[CC_OP_SHLB ... CC_OP_SHLQ] = USES_CC_DST | USES_CC_SRC,
[CC_OP_SARB ... CC_OP_SARQ] = USES_CC_DST | USES_CC_SRC,
[CC_OP_BMILGB ... CC_OP_BMILGQ] = USES_CC_DST | USES_CC_SRC,
[CC_OP_BLSIB ... CC_OP_BLSIQ] = USES_CC_DST | USES_CC_SRC,
[CC_OP_ADCX] = USES_CC_DST | USES_CC_SRC,
[CC_OP_ADOX] = USES_CC_SRC | USES_CC_SRC2,
[CC_OP_ADCOX] = USES_CC_DST | USES_CC_SRC | USES_CC_SRC2,
@ -865,6 +866,18 @@ static CCPrepare gen_prepare_sign_nz(TCGv src, MemOp size)
}
}
static CCPrepare gen_prepare_val_nz(TCGv src, MemOp size, bool eqz)
{
if (size == MO_TL) {
return (CCPrepare) { .cond = eqz ? TCG_COND_EQ : TCG_COND_NE,
.reg = src };
} else {
return (CCPrepare) { .cond = eqz ? TCG_COND_TSTEQ : TCG_COND_TSTNE,
.imm = MAKE_64BIT_MASK(0, 8 << size),
.reg = src };
}
}
/* compute eflags.C, trying to store it in reg if not NULL */
static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
{
@ -908,8 +921,11 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
case CC_OP_BMILGB ... CC_OP_BMILGQ:
size = s->cc_op - CC_OP_BMILGB;
gen_ext_tl(cpu_cc_src, cpu_cc_src, size, false);
return (CCPrepare) { .cond = TCG_COND_EQ, .reg = cpu_cc_src };
return gen_prepare_val_nz(cpu_cc_src, size, true);
case CC_OP_BLSIB ... CC_OP_BLSIQ:
size = s->cc_op - CC_OP_BLSIB;
return gen_prepare_val_nz(cpu_cc_src, size, false);
case CC_OP_ADCX:
case CC_OP_ADCOX:
@ -1006,12 +1022,7 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg)
default:
{
MemOp size = (s->cc_op - CC_OP_ADDB) & 3;
if (size == MO_TL) {
return (CCPrepare) { .cond = TCG_COND_EQ, .reg = cpu_cc_dst };
} else {
return (CCPrepare) { .cond = TCG_COND_TSTEQ, .reg = cpu_cc_dst,
.imm = (1ull << (8 << size)) - 1 };
}
return gen_prepare_val_nz(cpu_cc_dst, size, true);
}
}
}

1
tests/tcg/x86_64/Makefile.target
View File

@ -16,6 +16,7 @@ X86_64_TESTS += noexec
X86_64_TESTS += cmpxchg
X86_64_TESTS += adox
X86_64_TESTS += test-1648
X86_64_TESTS += test-2175
TESTS=$(MULTIARCH_TESTS) $(X86_64_TESTS) test-x86_64
else
TESTS=$(MULTIARCH_TESTS)

24
tests/tcg/x86_64/test-2175.c Normal file
View File

@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* See https://gitlab.com/qemu-project/qemu/-/issues/2185 */
#include <assert.h>
int test_setc(unsigned int x, unsigned int y)
{
asm("blsi %1, %0; setc %b0" : "+r"(x) : "r"(y));
return (unsigned char)x;
}
int test_pushf(unsigned int x, unsigned int y)
{
asm("blsi %1, %0; pushf; pop %q0" : "+r"(x) : "r"(y));
return x & 1;
}
int main()
{
assert(test_setc(1, 0xedbf530a));
assert(test_pushf(1, 0xedbf530a));
return 0;
}