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target/hppa: sar register allows only 5 bits on 32-bit CPU 

The sar shift amount register is limited to 5 bits when running
a 32-bit CPU. Strip off the remaining bits.

The interesting part is, that this register allows to detect at runtime
if a physical CPU is capable to execute PA2.0 (64-bit) instructions.

Signed-off-by: Helge Deller <deller@gmx.de>
This commit is contained in:
Helge Deller 2023-10-16 14:43:18 +02:00 committed by Richard Henderson
parent f13bf343cc
commit f3618f59f3
1 changed files with 2 additions and 2 deletions
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4
target/hppa/translate.c
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@ -2176,7 +2176,7 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a)
if (ctl == CR_SAR) { if (ctl == CR_SAR) {
reg = load_gpr(ctx, a->r); reg = load_gpr(ctx, a->r);
tmp = tcg_temp_new(); tmp = tcg_temp_new();
tcg_gen_andi_reg(tmp, reg, TARGET_REGISTER_BITS - 1); tcg_gen_andi_reg(tmp, reg, ctx->is_pa20 ? 63 : 31);
save_or_nullify(ctx, cpu_sar, tmp); save_or_nullify(ctx, cpu_sar, tmp);
cond_free(&ctx->null_cond); cond_free(&ctx->null_cond);
@ -2237,7 +2237,7 @@ static bool trans_mtsarcm(DisasContext *ctx, arg_mtsarcm *a)
TCGv_reg tmp = tcg_temp_new(); TCGv_reg tmp = tcg_temp_new();
tcg_gen_not_reg(tmp, load_gpr(ctx, a->r)); tcg_gen_not_reg(tmp, load_gpr(ctx, a->r));
tcg_gen_andi_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); tcg_gen_andi_reg(tmp, tmp, ctx->is_pa20 ? 63 : 31);
save_or_nullify(ctx, cpu_sar, tmp); save_or_nullify(ctx, cpu_sar, tmp);
cond_free(&ctx->null_cond); cond_free(&ctx->null_cond);