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tcg/loongarch64: Use cpuinfo.h 

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiajie Chen <c@jia.je>
Message-Id: <20230916220151.526140-5-richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-09-16 15:01:48 -07:00
parent 0885f1221e
commit f2a553481e
2 changed files with 5 additions and 11 deletions
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8
tcg/loongarch64/tcg-target.c.inc
View File

@ -32,8 +32,6 @@
#include "../tcg-ldst.c.inc" #include "../tcg-ldst.c.inc"
#include <asm/hwcap.h> #include <asm/hwcap.h>
bool use_lsx_instructions;
#ifdef CONFIG_DEBUG_TCG #ifdef CONFIG_DEBUG_TCG
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
"zero", "zero",
@ -2314,10 +2312,6 @@ static void tcg_target_init(TCGContext *s)
exit(EXIT_FAILURE); exit(EXIT_FAILURE);
} }
if (hwcap & HWCAP_LOONGARCH_LSX) {
use_lsx_instructions = 1;
}
tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS; tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
@ -2333,7 +2327,7 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8); tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9); tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9);
if (use_lsx_instructions) { if (cpuinfo & CPUINFO_LSX) {
tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V24); tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V24);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V25); tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V25);

8
tcg/loongarch64/tcg-target.h
View File

@ -29,6 +29,8 @@
#ifndef LOONGARCH_TCG_TARGET_H #ifndef LOONGARCH_TCG_TARGET_H
#define LOONGARCH_TCG_TARGET_H #define LOONGARCH_TCG_TARGET_H
#include "host/cpuinfo.h"
#define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_INSN_UNIT_SIZE 4
#define TCG_TARGET_NB_REGS 64 #define TCG_TARGET_NB_REGS 64
@ -85,8 +87,6 @@ typedef enum {
TCG_VEC_TMP0 = TCG_REG_V23, TCG_VEC_TMP0 = TCG_REG_V23,
} TCGReg; } TCGReg;
extern bool use_lsx_instructions;
/* used for function call generation */ /* used for function call generation */
#define TCG_REG_CALL_STACK TCG_REG_SP #define TCG_REG_CALL_STACK TCG_REG_SP
#define TCG_TARGET_STACK_ALIGN 16 #define TCG_TARGET_STACK_ALIGN 16
@ -171,10 +171,10 @@ extern bool use_lsx_instructions;
#define TCG_TARGET_HAS_muluh_i64 1 #define TCG_TARGET_HAS_muluh_i64 1
#define TCG_TARGET_HAS_mulsh_i64 1 #define TCG_TARGET_HAS_mulsh_i64 1
#define TCG_TARGET_HAS_qemu_ldst_i128 use_lsx_instructions #define TCG_TARGET_HAS_qemu_ldst_i128 (cpuinfo & CPUINFO_LSX)
#define TCG_TARGET_HAS_v64 0 #define TCG_TARGET_HAS_v64 0
#define TCG_TARGET_HAS_v128 use_lsx_instructions #define TCG_TARGET_HAS_v128 (cpuinfo & CPUINFO_LSX)
#define TCG_TARGET_HAS_v256 0 #define TCG_TARGET_HAS_v256 0
#define TCG_TARGET_HAS_not_vec 1 #define TCG_TARGET_HAS_not_vec 1