mirror of https://github.com/xemu-project/xemu.git
target/mips/mxu: Add S32CPS D16CPS Q8ABD Q16SAT insns
These instructions are part of pool2, see the grand tree above in the file. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-10-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Siarhei Volkau
Philippe Mathieu-Daudé
parent
bf1df65f0a
commit
f1e6547cfc
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@ -359,6 +359,7 @@ enum {
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OPC_MXU_S32MSUB = 0x04,
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OPC_MXU_S32MSUBU = 0x05,
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OPC_MXU__POOL01 = 0x06,
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OPC_MXU__POOL02 = 0x07,
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OPC_MXU_D16MUL = 0x08,
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OPC_MXU_D16MAC = 0x0A,
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OPC_MXU__POOL04 = 0x10,
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@ -405,6 +406,16 @@ enum {
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OPC_MXU_Q8ADD = 0x07,
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};
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/*
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* MXU pool 02
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*/
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enum {
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OPC_MXU_S32CPS = 0x00,
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OPC_MXU_D16CPS = 0x02,
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OPC_MXU_Q8ABD = 0x04,
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OPC_MXU_Q16SAT = 0x06,
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};
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/*
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* MXU pool 04 05 06 07 08 09 10 11
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*/
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@ -1675,12 +1686,155 @@ static void gen_mxu_q8avg(DisasContext *ctx, bool round45)
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/*
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* MXU instruction category: Arithmetic
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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* MXU instruction category: Addition and subtraction
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* Q8ADD
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* S32CPS D16CPS
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* Q8ADD
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*/
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/*
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* S32CPS
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* Update XRa if XRc < 0 by value of 0 - XRb
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* else XRa = XRb
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*/
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static void gen_mxu_S32CPS(DisasContext *ctx)
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{
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uint32_t pad, XRc, XRb, XRa;
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pad = extract32(ctx->opcode, 21, 5);
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XRc = extract32(ctx->opcode, 14, 4);
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XRb = extract32(ctx->opcode, 10, 4);
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XRa = extract32(ctx->opcode, 6, 4);
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if (unlikely(pad != 0)) {
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/* opcode padding incorrect -> do nothing */
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} else if (unlikely(XRa == 0)) {
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/* destination is zero register -> do nothing */
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} else if (unlikely(XRb == 0)) {
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/* XRc make no sense 0 - 0 = 0 -> just set destination to zero */
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tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
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} else if (unlikely(XRc == 0)) {
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/* condition always false -> just move XRb to XRa */
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tcg_gen_mov_tl(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
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} else {
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/* the most general case */
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TCGv t0 = tcg_temp_new();
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TCGLabel *l_not_less = gen_new_label();
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TCGLabel *l_done = gen_new_label();
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tcg_gen_brcondi_tl(TCG_COND_GE, mxu_gpr[XRc - 1], 0, l_not_less);
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tcg_gen_neg_tl(t0, mxu_gpr[XRb - 1]);
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tcg_gen_br(l_done);
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gen_set_label(l_not_less);
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gen_load_mxu_gpr(t0, XRb);
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gen_set_label(l_done);
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gen_store_mxu_gpr(t0, XRa);
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}
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}
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/*
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* D16CPS
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* Update XRa[0..1] if XRc[0..1] < 0 by value of 0 - XRb[0..1]
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* else XRa[0..1] = XRb[0..1]
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*/
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static void gen_mxu_D16CPS(DisasContext *ctx)
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{
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uint32_t pad, XRc, XRb, XRa;
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pad = extract32(ctx->opcode, 21, 5);
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XRc = extract32(ctx->opcode, 14, 4);
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XRb = extract32(ctx->opcode, 10, 4);
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XRa = extract32(ctx->opcode, 6, 4);
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if (unlikely(pad != 0)) {
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/* opcode padding incorrect -> do nothing */
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} else if (unlikely(XRa == 0)) {
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/* destination is zero register -> do nothing */
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} else if (unlikely(XRb == 0)) {
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/* XRc make no sense 0 - 0 = 0 -> just set destination to zero */
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tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
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} else if (unlikely(XRc == 0)) {
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/* condition always false -> just move XRb to XRa */
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tcg_gen_mov_tl(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
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} else {
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/* the most general case */
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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TCGLabel *l_done_hi = gen_new_label();
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TCGLabel *l_not_less_lo = gen_new_label();
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TCGLabel *l_done_lo = gen_new_label();
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tcg_gen_sextract_tl(t0, mxu_gpr[XRc - 1], 16, 16);
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tcg_gen_sextract_tl(t1, mxu_gpr[XRb - 1], 16, 16);
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tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l_done_hi);
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tcg_gen_subfi_tl(t1, 0, t1);
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gen_set_label(l_done_hi);
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tcg_gen_shli_i32(t1, t1, 16);
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tcg_gen_sextract_tl(t0, mxu_gpr[XRc - 1], 0, 16);
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tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l_not_less_lo);
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tcg_gen_sextract_tl(t0, mxu_gpr[XRb - 1], 0, 16);
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tcg_gen_subfi_tl(t0, 0, t0);
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tcg_gen_br(l_done_lo);
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gen_set_label(l_not_less_lo);
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tcg_gen_extract_tl(t0, mxu_gpr[XRb - 1], 0, 16);
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gen_set_label(l_done_lo);
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tcg_gen_deposit_tl(mxu_gpr[XRa - 1], t1, t0, 0, 16);
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}
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}
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/*
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* Q8ABD XRa, XRb, XRc
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* Gets absolute difference for quadruple of 8-bit
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* packed in XRb to another one in XRc,
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* put the result in XRa.
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* a.k.a. XRa[0..3] = abs(XRb[0..3] - XRc[0..3]);
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*/
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static void gen_mxu_Q8ABD(DisasContext *ctx)
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{
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uint32_t pad, XRc, XRb, XRa;
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pad = extract32(ctx->opcode, 21, 3);
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XRc = extract32(ctx->opcode, 14, 4);
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XRb = extract32(ctx->opcode, 10, 4);
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XRa = extract32(ctx->opcode, 6, 4);
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if (unlikely(pad != 0)) {
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/* opcode padding incorrect -> do nothing */
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} else if (unlikely(XRa == 0)) {
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/* destination is zero register -> do nothing */
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} else if (unlikely((XRb == 0) && (XRc == 0))) {
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/* both operands zero registers -> just set destination to zero */
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tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
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} else {
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/* the most general case */
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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TCGv t2 = tcg_temp_new();
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TCGv t3 = tcg_temp_new();
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TCGv t4 = tcg_temp_new();
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gen_load_mxu_gpr(t3, XRb);
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gen_load_mxu_gpr(t4, XRc);
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tcg_gen_movi_tl(t2, 0);
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for (int i = 0; i < 4; i++) {
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tcg_gen_extract_tl(t0, t3, 8 * i, 8);
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tcg_gen_extract_tl(t1, t4, 8 * i, 8);
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tcg_gen_sub_tl(t0, t0, t1);
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tcg_gen_abs_tl(t0, t0);
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tcg_gen_deposit_tl(t2, t2, t0, 8 * i, 8);
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}
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gen_store_mxu_gpr(t2, XRa);
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}
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}
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/*
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* Q8ADD XRa, XRb, XRc, ptn2
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* Add/subtract quadruple of 8-bit packed in XRb
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@ -1746,6 +1900,114 @@ static void gen_mxu_Q8ADD(DisasContext *ctx)
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}
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}
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/*
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* MXU instruction category: Miscellaneous
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* Q16SAT
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*/
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/*
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* Q16SAT XRa, XRb, XRc
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* Packs four 16-bit signed integers in XRb and XRc to
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* four saturated unsigned 8-bit into XRa.
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*
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*/
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static void gen_mxu_Q16SAT(DisasContext *ctx)
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{
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uint32_t pad, XRc, XRb, XRa;
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pad = extract32(ctx->opcode, 21, 3);
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XRc = extract32(ctx->opcode, 14, 4);
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XRb = extract32(ctx->opcode, 10, 4);
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XRa = extract32(ctx->opcode, 6, 4);
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if (unlikely(pad != 0)) {
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/* opcode padding incorrect -> do nothing */
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} else if (unlikely(XRa == 0)) {
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/* destination is zero register -> do nothing */
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} else {
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/* the most general case */
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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TCGv t2 = tcg_temp_new();
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tcg_gen_movi_tl(t2, 0);
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if (XRb != 0) {
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TCGLabel *l_less_hi = gen_new_label();
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TCGLabel *l_less_lo = gen_new_label();
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TCGLabel *l_lo = gen_new_label();
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TCGLabel *l_greater_hi = gen_new_label();
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TCGLabel *l_greater_lo = gen_new_label();
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TCGLabel *l_done = gen_new_label();
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tcg_gen_sari_tl(t0, mxu_gpr[XRb - 1], 16);
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tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l_less_hi);
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tcg_gen_brcondi_tl(TCG_COND_GT, t0, 255, l_greater_hi);
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tcg_gen_br(l_lo);
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gen_set_label(l_less_hi);
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tcg_gen_movi_tl(t0, 0);
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tcg_gen_br(l_lo);
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gen_set_label(l_greater_hi);
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tcg_gen_movi_tl(t0, 255);
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gen_set_label(l_lo);
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tcg_gen_shli_tl(t1, mxu_gpr[XRb - 1], 16);
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tcg_gen_sari_tl(t1, t1, 16);
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tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l_less_lo);
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tcg_gen_brcondi_tl(TCG_COND_GT, t1, 255, l_greater_lo);
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tcg_gen_br(l_done);
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gen_set_label(l_less_lo);
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tcg_gen_movi_tl(t1, 0);
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tcg_gen_br(l_done);
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gen_set_label(l_greater_lo);
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tcg_gen_movi_tl(t1, 255);
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gen_set_label(l_done);
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tcg_gen_shli_tl(t2, t0, 24);
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tcg_gen_shli_tl(t1, t1, 16);
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tcg_gen_or_tl(t2, t2, t1);
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}
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if (XRc != 0) {
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TCGLabel *l_less_hi = gen_new_label();
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TCGLabel *l_less_lo = gen_new_label();
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TCGLabel *l_lo = gen_new_label();
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TCGLabel *l_greater_hi = gen_new_label();
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TCGLabel *l_greater_lo = gen_new_label();
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TCGLabel *l_done = gen_new_label();
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tcg_gen_sari_tl(t0, mxu_gpr[XRc - 1], 16);
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tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l_less_hi);
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tcg_gen_brcondi_tl(TCG_COND_GT, t0, 255, l_greater_hi);
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tcg_gen_br(l_lo);
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gen_set_label(l_less_hi);
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tcg_gen_movi_tl(t0, 0);
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tcg_gen_br(l_lo);
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gen_set_label(l_greater_hi);
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tcg_gen_movi_tl(t0, 255);
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gen_set_label(l_lo);
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tcg_gen_shli_tl(t1, mxu_gpr[XRc - 1], 16);
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tcg_gen_sari_tl(t1, t1, 16);
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tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l_less_lo);
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tcg_gen_brcondi_tl(TCG_COND_GT, t1, 255, l_greater_lo);
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tcg_gen_br(l_done);
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gen_set_label(l_less_lo);
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tcg_gen_movi_tl(t1, 0);
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tcg_gen_br(l_done);
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gen_set_label(l_greater_lo);
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tcg_gen_movi_tl(t1, 255);
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gen_set_label(l_done);
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tcg_gen_shli_tl(t0, t0, 8);
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tcg_gen_or_tl(t2, t2, t0);
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tcg_gen_or_tl(t2, t2, t1);
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}
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gen_store_mxu_gpr(t2, XRa);
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}
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}
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/*
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* MXU instruction category: align
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@ -2085,6 +2347,31 @@ static void decode_opc_mxu__pool01(DisasContext *ctx)
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break;
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}
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}
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static void decode_opc_mxu__pool02(DisasContext *ctx)
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{
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uint32_t opcode = extract32(ctx->opcode, 18, 3);
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switch (opcode) {
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case OPC_MXU_S32CPS:
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gen_mxu_S32CPS(ctx);
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break;
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case OPC_MXU_D16CPS:
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gen_mxu_D16CPS(ctx);
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break;
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case OPC_MXU_Q8ABD:
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gen_mxu_Q8ABD(ctx);
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break;
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case OPC_MXU_Q16SAT:
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gen_mxu_Q16SAT(ctx);
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break;
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default:
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MIPS_INVAL("decode_opc_mxu");
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gen_reserved_instruction(ctx);
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break;
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}
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}
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static void decode_opc_mxu__pool04(DisasContext *ctx)
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{
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uint32_t reversed = extract32(ctx->opcode, 20, 1);
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@ -2334,6 +2621,9 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn)
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case OPC_MXU__POOL01:
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decode_opc_mxu__pool01(ctx);
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break;
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case OPC_MXU__POOL02:
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decode_opc_mxu__pool02(ctx);
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break;
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case OPC_MXU__POOL04:
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decode_opc_mxu__pool04(ctx);
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break;
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