mirror of https://github.com/xemu-project/xemu.git
pc,pci: bugfixes
Small bugfixes all over the place. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> -----BEGIN PGP SIGNATURE----- iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmEJp+sPHG1zdEByZWRo YXQuY29tAAoJECgfDbjSjVRpKuoH/inLOUmbyv9dxQL88qIfKUtDoVYWV1TspaR9 nswKltOZjLopLFZUMcfJsH5KxdM6CPM5d2/OQqMivKbwTxMSWQvfL+G/PdEqQ+Fb 21zkd483B6RhuLDeamSD2DGQImlZlpCOEVxucHxrnhsD9PqDGdMX4aYj1kfNcXnj 2X4apEPTMeeN8VAv0VgV6zXW1ksgAetVCKLuyktv6UerBT7yHAssGMPEX0j86TGX lg8nbtJ5LXMcCaY6vsBI/dSAhUmvilkvaIooTb7n604WgkUIHy1v7hDzACwZNyCP ZWDqz5oCtF7DIMKnHEzJlW7X7cxtmo151g4IVXBGYkuc+WXOVrU= =eYH0 -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging pc,pci: bugfixes Small bugfixes all over the place. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Tue 03 Aug 2021 21:32:43 BST # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: Drop _DSM 5 from expected DSDTs on ARM Revert "acpi/gpex: Inform os to keep firmware resource map" arm/acpi: allow DSDT changes acpi: x86: pcihp: add support hotplug on multifunction bridges hw/pcie-root-port: Fix hotplug for PCI devices requiring IO Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
f17d05569a
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@ -374,7 +374,7 @@ static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
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Aml *dev, *notify_method = NULL, *method;
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QObject *bsel;
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PCIBus *sec;
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int i;
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int devfn;
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bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
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if (bsel) {
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@ -384,23 +384,31 @@ static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
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notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
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}
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for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
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for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
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DeviceClass *dc;
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PCIDeviceClass *pc;
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PCIDevice *pdev = bus->devices[i];
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int slot = PCI_SLOT(i);
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PCIDevice *pdev = bus->devices[devfn];
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int slot = PCI_SLOT(devfn);
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int func = PCI_FUNC(devfn);
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/* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */
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int adr = slot << 16 | func;
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bool hotplug_enabled_dev;
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bool bridge_in_acpi;
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bool cold_plugged_bridge;
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if (!pdev) {
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if (bsel) { /* add hotplug slots for non present devices */
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/*
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* add hotplug slots for non present devices.
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* hotplug is supported only for non-multifunction device
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* so generate device description only for function 0
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*/
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if (bsel && !func) {
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if (pci_bus_is_express(bus) && slot > 0) {
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break;
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}
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dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
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dev = aml_device("S%.02X", devfn);
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aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
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aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
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aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
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method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
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aml_append(method,
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aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
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@ -436,9 +444,18 @@ static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
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continue;
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}
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/* start to compose PCI slot descriptor */
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dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
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aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
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/*
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* allow describing coldplugged bridges in ACPI even if they are not
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* on function 0, as they are not unpluggable, for all other devices
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* generate description only for function 0 per slot
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*/
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if (func && !bridge_in_acpi) {
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continue;
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}
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/* start to compose PCI device descriptor */
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dev = aml_device("S%.02X", devfn);
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aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
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if (bsel) {
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/*
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@ -496,7 +513,7 @@ static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
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build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
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}
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/* slot descriptor has been composed, add it into parent context */
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/* device descriptor has been composed, add it into parent context */
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aml_append(parent_scope, dev);
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}
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@ -525,13 +542,12 @@ static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
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/* Notify about child bus events in any case */
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if (pcihp_bridge_en) {
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QLIST_FOREACH(sec, &bus->child, sibling) {
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int32_t devfn = sec->parent_dev->devfn;
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if (pci_bus_is_root(sec)) {
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continue;
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}
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aml_append(method, aml_name("^S%.02X.PCNT", devfn));
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aml_append(method, aml_name("^S%.02X.PCNT",
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sec->parent_dev->devfn));
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}
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}
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@ -28,6 +28,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(GenPCIERootPort, GEN_PCIE_ROOT_PORT)
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(GEN_PCIE_ROOT_PORT_AER_OFFSET + PCI_ERR_SIZEOF)
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#define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR 1
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#define GEN_PCIE_ROOT_DEFAULT_IO_RANGE 4096
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struct GenPCIERootPort {
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/*< private >*/
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@ -75,6 +76,7 @@ static bool gen_rp_test_migrate_msix(void *opaque, int version_id)
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static void gen_rp_realize(DeviceState *dev, Error **errp)
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{
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PCIDevice *d = PCI_DEVICE(dev);
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PCIESlot *s = PCIE_SLOT(d);
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GenPCIERootPort *grp = GEN_PCIE_ROOT_PORT(d);
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PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);
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Error *local_err = NULL;
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@ -85,6 +87,9 @@ static void gen_rp_realize(DeviceState *dev, Error **errp)
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return;
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}
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if (grp->res_reserve.io == -1 && s->hotplug && !s->native_hotplug) {
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grp->res_reserve.io = GEN_PCIE_ROOT_DEFAULT_IO_RANGE;
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}
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int rc = pci_bridge_qemu_reserve_cap_init(d, 0,
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grp->res_reserve, errp);
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@ -112,26 +112,10 @@ static void acpi_dsdt_add_pci_osc(Aml *dev)
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UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
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ifctx = aml_if(aml_equal(aml_arg(0), UUID));
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ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
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uint8_t byte_list[] = {
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0x1 << 0 /* support for functions other than function 0 */ |
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0x1 << 5 /* support for function 5 */
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};
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buf = aml_buffer(ARRAY_SIZE(byte_list), byte_list);
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uint8_t byte_list[1] = {1};
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buf = aml_buffer(1, byte_list);
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aml_append(ifctx1, aml_return(buf));
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aml_append(ifctx, ifctx1);
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/*
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* PCI Firmware Specification 3.1
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* 4.6.5. _DSM for Ignoring PCI Boot Configurations
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*/
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/* Arg2: Function Index: 5 */
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ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(5)));
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/*
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* 0 - The operating system must not ignore the PCI configuration that
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* firmware has done at boot time.
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*/
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aml_append(ifctx1, aml_return(aml_int(0)));
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aml_append(ifctx, ifctx1);
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aml_append(method, ifctx);
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byte_list[0] = 0;
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