mirror of https://github.com/xemu-project/xemu.git
ETRAX serial port:
* Simulate basic interrupt driven serial io. * Connect to qemu char dev. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4300 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
edgar_igl
parent
b41f7df018
commit
f062058fa1
195
hw/etraxfs_ser.c
195
hw/etraxfs_ser.c
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@ -25,13 +25,66 @@
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#include <stdio.h>
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#include <ctype.h>
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#include "hw.h"
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#include "qemu-char.h"
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#define D(x)
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#define RW_TR_DMA_EN 0x04
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#define RW_DOUT 0x1c
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#define RW_STAT_DIN 0x20
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#define R_STAT_DIN 0x24
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#define RW_TR_CTRL 0x00
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#define RW_TR_DMA_EN 0x04
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#define RW_REC_CTRL 0x08
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#define RW_DOUT 0x1c
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#define RS_STAT_DIN 0x20
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#define R_STAT_DIN 0x24
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#define RW_INTR_MASK 0x2c
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#define RW_ACK_INTR 0x30
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#define R_INTR 0x34
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#define R_MASKED_INTR 0x38
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#define STAT_DAV 16
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#define STAT_TR_IDLE 22
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#define STAT_TR_RDY 24
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struct etrax_serial_t
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{
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CPUState *env;
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CharDriverState *chr;
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qemu_irq *irq;
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target_phys_addr_t base;
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int pending_tx;
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/* Control registers. */
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uint32_t rw_tr_ctrl;
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uint32_t rw_tr_dma_en;
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uint32_t rw_rec_ctrl;
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uint32_t rs_stat_din;
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uint32_t r_stat_din;
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uint32_t rw_intr_mask;
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uint32_t rw_ack_intr;
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uint32_t r_intr;
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uint32_t r_masked_intr;
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};
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static void ser_update_irq(struct etrax_serial_t *s)
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{
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uint32_t o_irq = s->r_masked_intr;
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s->r_intr &= ~(s->rw_ack_intr);
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s->r_masked_intr = s->r_intr & s->rw_intr_mask;
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if (o_irq != s->r_masked_intr) {
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D(printf("irq_mask=%x r_intr=%x rmi=%x airq=%x \n",
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s->rw_intr_mask, s->r_intr,
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s->r_masked_intr, s->rw_ack_intr));
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if (s->r_masked_intr)
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qemu_irq_raise(s->irq[0]);
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else
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qemu_irq_lower(s->irq[0]);
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}
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s->rw_ack_intr = 0;
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}
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static uint32_t ser_readb (void *opaque, target_phys_addr_t addr)
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{
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@ -39,25 +92,43 @@ static uint32_t ser_readb (void *opaque, target_phys_addr_t addr)
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D(printf ("%s %x pc=%x\n", __func__, addr, env->pc));
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return 0;
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}
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static uint32_t ser_readw (void *opaque, target_phys_addr_t addr)
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{
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D(CPUState *env = opaque);
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D(printf ("%s %x pc=%x\n", __func__, addr, env->pc));
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return 0;
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}
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static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
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{
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D(CPUState *env = opaque);
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struct etrax_serial_t *s = opaque;
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D(CPUState *env = s->env);
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uint32_t r = 0;
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switch (addr & 0xfff)
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{
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case RW_TR_CTRL:
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r = s->rw_tr_ctrl;
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break;
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case RW_TR_DMA_EN:
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r = s->rw_tr_dma_en;
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break;
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case RS_STAT_DIN:
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r = s->rs_stat_din;
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/* clear dav. */
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s->rs_stat_din &= ~(1 << STAT_DAV);
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break;
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case R_STAT_DIN:
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r |= 1 << 24; /* set tr_rdy. */
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r |= 1 << 22; /* set tr_idle. */
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r = s->rs_stat_din;
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break;
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case RW_ACK_INTR:
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D(printf("load rw_ack_intr=%x\n", s->rw_ack_intr));
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r = s->rw_ack_intr;
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break;
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case RW_INTR_MASK:
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r = s->rw_intr_mask;
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break;
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case R_INTR:
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D(printf("load r_intr=%x\n", s->r_intr));
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r = s->r_intr;
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break;
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case R_MASKED_INTR:
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D(printf("load r_maked_intr=%x\n", s->r_masked_intr));
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r = s->r_masked_intr;
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break;
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default:
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@ -70,53 +141,117 @@ static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
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static void
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ser_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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D(CPUState *env = opaque);
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D(struct etrax_serial_t *s = opaque);
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D(CPUState *env = s->env);
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D(printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc));
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}
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static void
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ser_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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D(CPUState *env = opaque);
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D(printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc));
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}
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static void
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ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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D(CPUState *env = opaque);
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struct etrax_serial_t *s = opaque;
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unsigned char ch = value;
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D(CPUState *env = s->env);
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switch (addr & 0xfff)
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{
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case RW_TR_CTRL:
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D(printf("rw_tr_ctrl=%x\n", value));
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s->rw_tr_ctrl = value;
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break;
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case RW_TR_DMA_EN:
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D(printf("rw_tr_dma_en=%x\n", value));
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s->rw_tr_dma_en = value;
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break;
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case RW_DOUT:
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if (isprint(value) || isspace(value))
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putchar(value);
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else
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putchar('.');
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fflush(stdout);
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qemu_chr_write(s->chr, &ch, 1);
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s->r_intr |= 1;
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s->pending_tx = 1;
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break;
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case RW_ACK_INTR:
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D(printf("rw_ack_intr=%x\n", value));
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s->rw_ack_intr = value;
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if (s->pending_tx && (s->rw_ack_intr & 1)) {
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s->r_intr |= 1;
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s->pending_tx = 0;
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s->rw_ack_intr &= ~1;
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}
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break;
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case RW_INTR_MASK:
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D(printf("r_intr_mask=%x\n", value));
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s->rw_intr_mask = value;
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break;
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default:
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D(printf ("%s %x %x pc=%x\n",
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__func__, addr, value, env->pc));
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break;
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}
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ser_update_irq(s);
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}
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static CPUReadMemoryFunc *ser_read[] = {
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&ser_readb,
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&ser_readw,
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&ser_readb,
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&ser_readl,
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};
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static CPUWriteMemoryFunc *ser_write[] = {
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&ser_writeb,
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&ser_writew,
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&ser_writeb,
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&ser_writel,
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};
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void etraxfs_ser_init(CPUState *env, qemu_irq *irqs, target_phys_addr_t base)
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static void serial_receive(void *opaque, const uint8_t *buf, int size)
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{
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struct etrax_serial_t *s = opaque;
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s->r_intr |= 8;
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s->rs_stat_din &= ~0xff;
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s->rs_stat_din |= (buf[0] & 0xff);
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s->rs_stat_din |= (1 << STAT_DAV); /* dav. */
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ser_update_irq(s);
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}
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static int serial_can_receive(void *opaque)
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{
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struct etrax_serial_t *s = opaque;
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int r;
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/* Is the receiver enabled? */
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r = s->rw_rec_ctrl & 1;
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/* Pending rx data? */
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r |= !(s->r_intr & 8);
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return r;
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}
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static void serial_event(void *opaque, int event)
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{
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}
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void etraxfs_ser_init(CPUState *env, qemu_irq *irq, CharDriverState *chr,
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target_phys_addr_t base)
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{
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struct etrax_serial_t *s;
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int ser_regs;
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ser_regs = cpu_register_io_memory(0, ser_read, ser_write, env);
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s = qemu_mallocz(sizeof *s);
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if (!s)
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return;
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s->env = env;
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s->irq = irq;
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s->base = base;
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s->chr = chr;
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/* transmitter begins ready and idle. */
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s->rs_stat_din |= (1 << STAT_TR_RDY);
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s->rs_stat_din |= (1 << STAT_TR_IDLE);
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qemu_chr_add_handlers(chr, serial_can_receive, serial_receive,
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serial_event, s);
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ser_regs = cpu_register_io_memory(0, ser_read, ser_write, s);
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cpu_register_physical_memory (base, 0x3c, ser_regs);
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}
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