mirror of https://github.com/xemu-project/xemu.git
target/arm: Add SVE to migration state
Save the high parts of the Zregs and all of the Pregs. The ZCR_ELx registers are migrated via the CP mechanism. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180123035349.24538-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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target/arm
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@ -122,6 +122,56 @@ static const VMStateDescription vmstate_iwmmxt = {
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}
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}
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};
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};
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#ifdef TARGET_AARCH64
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/* The expression ARM_MAX_VQ - 2 is 0 for pure AArch32 build,
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* and ARMPredicateReg is actively empty. This triggers errors
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* in the expansion of the VMSTATE macros.
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*/
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static bool sve_needed(void *opaque)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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return arm_feature(env, ARM_FEATURE_SVE);
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}
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/* The first two words of each Zreg is stored in VFP state. */
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static const VMStateDescription vmstate_zreg_hi_reg = {
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.name = "cpu/sve/zreg_hi",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64_SUB_ARRAY(d, ARMVectorReg, 2, ARM_MAX_VQ - 2),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_preg_reg = {
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.name = "cpu/sve/preg",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64_ARRAY(p, ARMPredicateReg, 2 * ARM_MAX_VQ / 8),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_sve = {
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.name = "cpu/sve",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = sve_needed,
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.fields = (VMStateField[]) {
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VMSTATE_STRUCT_ARRAY(env.vfp.zregs, ARMCPU, 32, 0,
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vmstate_zreg_hi_reg, ARMVectorReg),
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VMSTATE_STRUCT_ARRAY(env.vfp.pregs, ARMCPU, 17, 0,
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vmstate_preg_reg, ARMPredicateReg),
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VMSTATE_END_OF_LIST()
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}
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};
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#endif /* AARCH64 */
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static bool m_needed(void *opaque)
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static bool m_needed(void *opaque)
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{
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{
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ARMCPU *cpu = opaque;
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ARMCPU *cpu = opaque;
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@ -586,6 +636,9 @@ const VMStateDescription vmstate_arm_cpu = {
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&vmstate_pmsav7,
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&vmstate_pmsav7,
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&vmstate_pmsav8,
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&vmstate_pmsav8,
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&vmstate_m_security,
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&vmstate_m_security,
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#ifdef TARGET_AARCH64
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&vmstate_sve,
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#endif
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NULL
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NULL
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}
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}
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};
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};
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