mirror of https://github.com/xemu-project/xemu.git
target/arm: Add RME cpregs
This includes GPCCR, GPTBR, MFAR, the TLB flush insns PAALL, PAALLOS, RPALOS, RPAOS, and the cache flush insns CIPAPA and CIGDPAPA. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230620124418.805717-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -541,6 +541,11 @@ typedef struct CPUArchState {
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uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */
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uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */
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uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */
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uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */
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uint64_t fgt_exec[1]; /* HFGITR */
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uint64_t fgt_exec[1]; /* HFGITR */
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/* RME registers */
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uint64_t gpccr_el3;
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uint64_t gptbr_el3;
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uint64_t mfar_el3;
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} cp15;
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} cp15;
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struct {
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struct {
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@ -1055,6 +1060,7 @@ struct ArchCPU {
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uint64_t reset_cbar;
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uint64_t reset_cbar;
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uint32_t reset_auxcr;
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uint32_t reset_auxcr;
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bool reset_hivecs;
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bool reset_hivecs;
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uint8_t reset_l0gptsz;
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/*
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/*
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* Intermediate values used during property parsing.
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* Intermediate values used during property parsing.
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@ -2341,6 +2347,19 @@ FIELD(MVFR1, SIMDFMAC, 28, 4)
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FIELD(MVFR2, SIMDMISC, 0, 4)
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FIELD(MVFR2, SIMDMISC, 0, 4)
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FIELD(MVFR2, FPMISC, 4, 4)
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FIELD(MVFR2, FPMISC, 4, 4)
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FIELD(GPCCR, PPS, 0, 3)
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FIELD(GPCCR, IRGN, 8, 2)
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FIELD(GPCCR, ORGN, 10, 2)
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FIELD(GPCCR, SH, 12, 2)
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FIELD(GPCCR, PGS, 14, 2)
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FIELD(GPCCR, GPC, 16, 1)
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FIELD(GPCCR, GPCP, 17, 1)
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FIELD(GPCCR, L0GPTSZ, 20, 4)
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FIELD(MFAR, FPA, 12, 40)
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FIELD(MFAR, NSE, 62, 1)
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FIELD(MFAR, NS, 63, 1)
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QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
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QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
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/* If adding a feature bit which corresponds to a Linux ELF
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/* If adding a feature bit which corresponds to a Linux ELF
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@ -6910,6 +6910,83 @@ static const ARMCPRegInfo sme_reginfo[] = {
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.access = PL2_RW, .accessfn = access_esm,
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.access = PL2_RW, .accessfn = access_esm,
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.type = ARM_CP_CONST, .resetvalue = 0 },
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.type = ARM_CP_CONST, .resetvalue = 0 },
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};
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};
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static void tlbi_aa64_paall_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = env_cpu(env);
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tlb_flush(cs);
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}
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static void gpccr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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/* L0GPTSZ is RO; other bits not mentioned are RES0. */
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uint64_t rw_mask = R_GPCCR_PPS_MASK | R_GPCCR_IRGN_MASK |
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R_GPCCR_ORGN_MASK | R_GPCCR_SH_MASK | R_GPCCR_PGS_MASK |
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R_GPCCR_GPC_MASK | R_GPCCR_GPCP_MASK;
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env->cp15.gpccr_el3 = (value & rw_mask) | (env->cp15.gpccr_el3 & ~rw_mask);
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}
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static void gpccr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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env->cp15.gpccr_el3 = FIELD_DP64(0, GPCCR, L0GPTSZ,
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env_archcpu(env)->reset_l0gptsz);
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}
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static void tlbi_aa64_paallos_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = env_cpu(env);
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tlb_flush_all_cpus_synced(cs);
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}
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static const ARMCPRegInfo rme_reginfo[] = {
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{ .name = "GPCCR_EL3", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 6,
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.access = PL3_RW, .writefn = gpccr_write, .resetfn = gpccr_reset,
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.fieldoffset = offsetof(CPUARMState, cp15.gpccr_el3) },
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{ .name = "GPTBR_EL3", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 4,
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.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.gptbr_el3) },
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{ .name = "MFAR_EL3", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 5,
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.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mfar_el3) },
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{ .name = "TLBI_PAALL", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 4,
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.access = PL3_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_paall_write },
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{ .name = "TLBI_PAALLOS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 4,
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.access = PL3_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_paallos_write },
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/*
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* QEMU does not have a way to invalidate by physical address, thus
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* invalidating a range of physical addresses is accomplished by
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* flushing all tlb entries in the outer sharable domain,
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* just like PAALLOS.
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*/
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{ .name = "TLBI_RPALOS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 4, .opc2 = 7,
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.access = PL3_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_paallos_write },
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{ .name = "TLBI_RPAOS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 4, .opc2 = 3,
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.access = PL3_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_paallos_write },
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{ .name = "DC_CIPAPA", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 6, .crn = 7, .crm = 14, .opc2 = 1,
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.access = PL3_W, .type = ARM_CP_NOP },
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};
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static const ARMCPRegInfo rme_mte_reginfo[] = {
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{ .name = "DC_CIGDPAPA", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 6, .crn = 7, .crm = 14, .opc2 = 5,
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.access = PL3_W, .type = ARM_CP_NOP },
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};
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#endif /* TARGET_AARCH64 */
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#endif /* TARGET_AARCH64 */
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static void define_pmu_regs(ARMCPU *cpu)
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static void define_pmu_regs(ARMCPU *cpu)
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@ -9130,6 +9207,13 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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if (cpu_isar_feature(aa64_fgt, cpu)) {
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if (cpu_isar_feature(aa64_fgt, cpu)) {
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define_arm_cp_regs(cpu, fgt_reginfo);
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define_arm_cp_regs(cpu, fgt_reginfo);
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}
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}
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if (cpu_isar_feature(aa64_rme, cpu)) {
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define_arm_cp_regs(cpu, rme_reginfo);
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if (cpu_isar_feature(aa64_mte, cpu)) {
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define_arm_cp_regs(cpu, rme_mte_reginfo);
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}
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}
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#endif
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#endif
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if (cpu_isar_feature(any_predinv, cpu)) {
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if (cpu_isar_feature(any_predinv, cpu)) {
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