mirror of https://github.com/xemu-project/xemu.git
accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu
We have replaced tlb_fill with record_sigsegv for user mode. Move the declaration to restrict it to system emulation. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
parent
6407f64fcf
commit
eeca7dc566
|
@ -35,18 +35,6 @@ struct TCGCPUOps {
|
||||||
void (*cpu_exec_enter)(CPUState *cpu);
|
void (*cpu_exec_enter)(CPUState *cpu);
|
||||||
/** @cpu_exec_exit: Callback for cpu_exec cleanup */
|
/** @cpu_exec_exit: Callback for cpu_exec cleanup */
|
||||||
void (*cpu_exec_exit)(CPUState *cpu);
|
void (*cpu_exec_exit)(CPUState *cpu);
|
||||||
/**
|
|
||||||
* @tlb_fill: Handle a softmmu tlb miss or user-only address fault
|
|
||||||
*
|
|
||||||
* For system mode, if the access is valid, call tlb_set_page
|
|
||||||
* and return true; if the access is invalid, and probe is
|
|
||||||
* true, return false; otherwise raise an exception and do
|
|
||||||
* not return. For user-only mode, always raise an exception
|
|
||||||
* and do not return.
|
|
||||||
*/
|
|
||||||
bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
|
|
||||||
MMUAccessType access_type, int mmu_idx,
|
|
||||||
bool probe, uintptr_t retaddr);
|
|
||||||
/** @debug_excp_handler: Callback for handling debug exceptions */
|
/** @debug_excp_handler: Callback for handling debug exceptions */
|
||||||
void (*debug_excp_handler)(CPUState *cpu);
|
void (*debug_excp_handler)(CPUState *cpu);
|
||||||
|
|
||||||
|
@ -68,6 +56,16 @@ struct TCGCPUOps {
|
||||||
#ifdef CONFIG_SOFTMMU
|
#ifdef CONFIG_SOFTMMU
|
||||||
/** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
|
/** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
|
||||||
bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
|
bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
|
||||||
|
/**
|
||||||
|
* @tlb_fill: Handle a softmmu tlb miss
|
||||||
|
*
|
||||||
|
* If the access is valid, call tlb_set_page and return true;
|
||||||
|
* if the access is invalid and probe is true, return false;
|
||||||
|
* otherwise raise an exception and do not return.
|
||||||
|
*/
|
||||||
|
bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
|
||||||
|
MMUAccessType access_type, int mmu_idx,
|
||||||
|
bool probe, uintptr_t retaddr);
|
||||||
/**
|
/**
|
||||||
* @do_transaction_failed: Callback for handling failed memory transactions
|
* @do_transaction_failed: Callback for handling failed memory transactions
|
||||||
* (ie bus faults or external aborts; not MMU faults)
|
* (ie bus faults or external aborts; not MMU faults)
|
||||||
|
|
|
@ -697,9 +697,6 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
|
||||||
|
|
||||||
if (tcg_ops->record_sigsegv) {
|
if (tcg_ops->record_sigsegv) {
|
||||||
tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra);
|
tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra);
|
||||||
} else if (tcg_ops->tlb_fill) {
|
|
||||||
tcg_ops->tlb_fill(cpu, addr, 0, access_type, MMU_USER_IDX, false, ra);
|
|
||||||
g_assert_not_reached();
|
|
||||||
}
|
}
|
||||||
|
|
||||||
force_sig_fault(TARGET_SIGSEGV,
|
force_sig_fault(TARGET_SIGSEGV,
|
||||||
|
|
Loading…
Reference in New Issue