ShuriZma
/
xemu
mirror of https://github.com/xemu-project/xemu.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

hw/nvme: generalize the mbar size helper 

Generalize the mbar size helper such that it can handle cases where the
MSI-X table and PBA are expected to be in an exclusive bar.

Cc: qemu-stable@nongnu.org
Reviewed-by: Jesper Wendel Devantier <foss@defmacro.it>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
This commit is contained in:
Klaus Jensen 2024-03-10 11:39:25 +01:00
parent bdc31646c5
commit ee7bda4d38
1 changed files with 16 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
hw/nvme/ctrl.c
View File

@ -8015,13 +8015,18 @@ static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev)
memory_region_set_enabled(&n->pmr.dev->mr, false); memory_region_set_enabled(&n->pmr.dev->mr, false);
} }
static uint64_t nvme_bar_size(unsigned total_queues, unsigned total_irqs, static uint64_t nvme_mbar_size(unsigned total_queues, unsigned total_irqs,
unsigned *msix_table_offset, unsigned *msix_table_offset,
unsigned *msix_pba_offset) unsigned *msix_pba_offset)
{ {
uint64_t bar_size, msix_table_size, msix_pba_size; uint64_t bar_size, msix_table_size;
bar_size = sizeof(NvmeBar) + 2 * total_queues * NVME_DB_SIZE; bar_size = sizeof(NvmeBar) + 2 * total_queues * NVME_DB_SIZE;
if (total_irqs == 0) {
goto out;
}
bar_size = QEMU_ALIGN_UP(bar_size, 4 * KiB); bar_size = QEMU_ALIGN_UP(bar_size, 4 * KiB);
if (msix_table_offset) { if (msix_table_offset) {
@ -8036,11 +8041,10 @@ static uint64_t nvme_bar_size(unsigned total_queues, unsigned total_irqs,
*msix_pba_offset = bar_size; *msix_pba_offset = bar_size;
} }
msix_pba_size = QEMU_ALIGN_UP(total_irqs, 64) / 8; bar_size += QEMU_ALIGN_UP(total_irqs, 64) / 8;
bar_size += msix_pba_size;
bar_size = pow2ceil(bar_size); out:
return bar_size; return pow2ceil(bar_size);
} }
static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *pci_dev, uint16_t offset) static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *pci_dev, uint16_t offset)
@ -8048,7 +8052,7 @@ static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *pci_dev, uint16_t offset)
uint16_t vf_dev_id = n->params.use_intel_id ? uint16_t vf_dev_id = n->params.use_intel_id ?
PCI_DEVICE_ID_INTEL_NVME : PCI_DEVICE_ID_REDHAT_NVME; PCI_DEVICE_ID_INTEL_NVME : PCI_DEVICE_ID_REDHAT_NVME;
NvmePriCtrlCap *cap = &n->pri_ctrl_cap; NvmePriCtrlCap *cap = &n->pri_ctrl_cap;
uint64_t bar_size = nvme_bar_size(le16_to_cpu(cap->vqfrsm), uint64_t bar_size = nvme_mbar_size(le16_to_cpu(cap->vqfrsm),
le16_to_cpu(cap->vifrsm), le16_to_cpu(cap->vifrsm),
NULL, NULL); NULL, NULL);
@ -8087,7 +8091,7 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
ERRP_GUARD(); ERRP_GUARD();
uint8_t *pci_conf = pci_dev->config; uint8_t *pci_conf = pci_dev->config;
uint64_t bar_size; uint64_t bar_size;
unsigned msix_table_offset, msix_pba_offset; unsigned msix_table_offset = 0, msix_pba_offset = 0;
int ret; int ret;
pci_conf[PCI_INTERRUPT_PIN] = 1; pci_conf[PCI_INTERRUPT_PIN] = 1;
@ -8110,7 +8114,7 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
} }
/* add one to max_ioqpairs to account for the admin queue pair */ /* add one to max_ioqpairs to account for the admin queue pair */
bar_size = nvme_bar_size(n->params.max_ioqpairs + 1, n->params.msix_qsize, bar_size = nvme_mbar_size(n->params.max_ioqpairs + 1, n->params.msix_qsize,
&msix_table_offset, &msix_pba_offset); &msix_table_offset, &msix_pba_offset);
memory_region_init(&n->bar0, OBJECT(n), "nvme-bar0", bar_size); memory_region_init(&n->bar0, OBJECT(n), "nvme-bar0", bar_size);