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target/loongarch: Implement xavg/xvagr 

This patch includes:
- XVAVG.{B/H/W/D/}[U];
- XVAVGR.{B/H/W/D}[U].

Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914022645.1151356-22-gaosong@loongson.cn>
This commit is contained in:
Song Gao 2023-09-14 10:26:09 +08:00
parent 85995f076a
commit ee7250d091
No known key found for this signature in database
GPG Key ID: 40A2FFF239263EDF
4 changed files with 62 additions and 10 deletions
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17
target/loongarch/disas.c
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@ -1825,6 +1825,23 @@ INSN_LASX(xvaddwod_w_hu_h, vvv)
INSN_LASX(xvaddwod_d_wu_w, vvv)
INSN_LASX(xvaddwod_q_du_d, vvv)
INSN_LASX(xvavg_b, vvv)
INSN_LASX(xvavg_h, vvv)
INSN_LASX(xvavg_w, vvv)
INSN_LASX(xvavg_d, vvv)
INSN_LASX(xvavg_bu, vvv)
INSN_LASX(xvavg_hu, vvv)
INSN_LASX(xvavg_wu, vvv)
INSN_LASX(xvavg_du, vvv)
INSN_LASX(xvavgr_b, vvv)
INSN_LASX(xvavgr_h, vvv)
INSN_LASX(xvavgr_w, vvv)
INSN_LASX(xvavgr_d, vvv)
INSN_LASX(xvavgr_bu, vvv)
INSN_LASX(xvavgr_hu, vvv)
INSN_LASX(xvavgr_wu, vvv)
INSN_LASX(xvavgr_du, vvv)
INSN_LASX(xvreplgr2vr_b, vr)
INSN_LASX(xvreplgr2vr_h, vr)
INSN_LASX(xvreplgr2vr_w, vr)

16
target/loongarch/insn_trans/trans_vec.c.inc
View File

@ -1419,6 +1419,14 @@ TRANS(vavg_bu, LSX, gvec_vvv, MO_8, do_vavg_u)
TRANS(vavg_hu, LSX, gvec_vvv, MO_16, do_vavg_u)
TRANS(vavg_wu, LSX, gvec_vvv, MO_32, do_vavg_u)
TRANS(vavg_du, LSX, gvec_vvv, MO_64, do_vavg_u)
TRANS(xvavg_b, LASX, gvec_xxx, MO_8, do_vavg_s)
TRANS(xvavg_h, LASX, gvec_xxx, MO_16, do_vavg_s)
TRANS(xvavg_w, LASX, gvec_xxx, MO_32, do_vavg_s)
TRANS(xvavg_d, LASX, gvec_xxx, MO_64, do_vavg_s)
TRANS(xvavg_bu, LASX, gvec_xxx, MO_8, do_vavg_u)
TRANS(xvavg_hu, LASX, gvec_xxx, MO_16, do_vavg_u)
TRANS(xvavg_wu, LASX, gvec_xxx, MO_32, do_vavg_u)
TRANS(xvavg_du, LASX, gvec_xxx, MO_64, do_vavg_u)
static void do_vavgr_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz)
@ -1500,6 +1508,14 @@ TRANS(vavgr_bu, LSX, gvec_vvv, MO_8, do_vavgr_u)
TRANS(vavgr_hu, LSX, gvec_vvv, MO_16, do_vavgr_u)
TRANS(vavgr_wu, LSX, gvec_vvv, MO_32, do_vavgr_u)
TRANS(vavgr_du, LSX, gvec_vvv, MO_64, do_vavgr_u)
TRANS(xvavgr_b, LASX, gvec_xxx, MO_8, do_vavgr_s)
TRANS(xvavgr_h, LASX, gvec_xxx, MO_16, do_vavgr_s)
TRANS(xvavgr_w, LASX, gvec_xxx, MO_32, do_vavgr_s)
TRANS(xvavgr_d, LASX, gvec_xxx, MO_64, do_vavgr_s)
TRANS(xvavgr_bu, LASX, gvec_xxx, MO_8, do_vavgr_u)
TRANS(xvavgr_hu, LASX, gvec_xxx, MO_16, do_vavgr_u)
TRANS(xvavgr_wu, LASX, gvec_xxx, MO_32, do_vavgr_u)
TRANS(xvavgr_du, LASX, gvec_xxx, MO_64, do_vavgr_u)
static void gen_vabsd_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
{

17
target/loongarch/insns.decode
View File

@ -1406,6 +1406,23 @@ xvaddwod_w_hu_h 0111 01000100 00001 ..... ..... ..... @vvv
xvaddwod_d_wu_w 0111 01000100 00010 ..... ..... ..... @vvv
xvaddwod_q_du_d 0111 01000100 00011 ..... ..... ..... @vvv
xvavg_b 0111 01000110 01000 ..... ..... ..... @vvv
xvavg_h 0111 01000110 01001 ..... ..... ..... @vvv
xvavg_w 0111 01000110 01010 ..... ..... ..... @vvv
xvavg_d 0111 01000110 01011 ..... ..... ..... @vvv
xvavg_bu 0111 01000110 01100 ..... ..... ..... @vvv
xvavg_hu 0111 01000110 01101 ..... ..... ..... @vvv
xvavg_wu 0111 01000110 01110 ..... ..... ..... @vvv
xvavg_du 0111 01000110 01111 ..... ..... ..... @vvv
xvavgr_b 0111 01000110 10000 ..... ..... ..... @vvv
xvavgr_h 0111 01000110 10001 ..... ..... ..... @vvv
xvavgr_w 0111 01000110 10010 ..... ..... ..... @vvv
xvavgr_d 0111 01000110 10011 ..... ..... ..... @vvv
xvavgr_bu 0111 01000110 10100 ..... ..... ..... @vvv
xvavgr_hu 0111 01000110 10101 ..... ..... ..... @vvv
xvavgr_wu 0111 01000110 10110 ..... ..... ..... @vvv
xvavgr_du 0111 01000110 10111 ..... ..... ..... @vvv
xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr

22
target/loongarch/vec_helper.c
View File

@ -350,16 +350,18 @@ DO_ODD_U_S(vaddwod_d_wu_w, 64, D, UD, W, UW, DO_ADD)
#define DO_VAVG(a, b) ((a >> 1) + (b >> 1) + (a & b & 1))
#define DO_VAVGR(a, b) ((a >> 1) + (b >> 1) + ((a | b) & 1))
#define DO_3OP(NAME, BIT, E, DO_OP) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t v) \
{ \
int i; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
for (i = 0; i < LSX_LEN/BIT; i++) { \
Vd->E(i) = DO_OP(Vj->E(i), Vk->E(i)); \
} \
#define DO_3OP(NAME, BIT, E, DO_OP) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \
int i; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < oprsz / (BIT / 8); i++) { \
Vd->E(i) = DO_OP(Vj->E(i), Vk->E(i)); \
} \
}
DO_3OP(vavg_b, 8, B, DO_VAVG)