ShuriZma
/
xemu
mirror of https://github.com/xemu-project/xemu.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

MIPS queue for October 24th, 2019 - v2 

-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJdsyTJAAoJENSXKoln91pl9sAIAJI/O4zM9qASkiNkLdazMUcf
 pDGp/hGrNTZclakNSB8+PqEFP3mfSBtr8Wy6Nrw83iIzXkoXHW7zoH+FR3R9OIBB
 TGEB/eGuW/oa1EQZDteF6C6ZnCC3nHmuxHjPPQq0b8JzZmCWHAG0Ub0vvcGzxi0h
 U1kf372KKkyG+or1fCrlnVwuXA6RrhASbIA3tyFhei6EdVdyJ8dU6c6iu/A1G0fh
 e7G3KNXciQJo8jts67O702CiWYwWn2o32rD4x7BO2dWg0Ih6spBnxGiMfbpf/7U8
 hWmfWFIc/0yCmxukItWiocDcyxslWrQq2letPKHlBBxdj9/Tyojf5PCHz9iaODs=
 =1VjK
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-oct-24-2019-v2' into staging

MIPS queue for October 24th, 2019 - v2

# gpg: Signature made Fri 25 Oct 2019 17:37:29 BST
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-oct-24-2019-v2:
  tests/ssh_linux_malta: Fix 64-bit target tests
  tests/ssh_linux_malta: Refactor how to get image/kernel info
  tests/ssh_linux_malta: Match stricter console output
  tests/ssh_linux_malta: Remove duplicated test
  tests/ssh_linux_malta: Run tests using a snapshot image
  target/mips: Refactor handling of vector compare 'less than' (signed) instructions
  target/mips: Refactor handling of vector compare 'equal' instructions
  target/mips: Demacro LMI decoder
  target/mips: msa: Split helpers for ASUB_<S|U>.<B|H|W|D>
  target/mips: msa: Split helpers for HSUB_<S|U>.<H|W|D>
  target/mips: msa: Split helpers for PCK<EV|OD>.<B|H|W|D>
  target/mips: msa: Split helpers for S<LL|RA|RAR|RL|RLR>.<B|H|W|D>
  target/mips: msa: Split helpers for HADD_<S|U>.<H|W|D>
  target/mips: msa: Split helpers for ADD<_A|S_A|S_S|S_U|V>.<B|H|W|D>
  target/mips: msa: Split helpers for ILV<EV|OD|L|R>.<B|H|W|D>
  target/mips: msa: Split helpers for <MAX|MIN>_<S|U>.<B|H|W|D>
  target/mips: msa: Split helpers for <MAX|MIN>_A.<B|H|W|D>
  MAINTAINERS: Update mail address of Aleksandar Rikalo
  target/mips: Clean up op_helper.c
  target/mips: Clean up helper.c

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2019-10-25 18:32:26 +01:00
parent 03bf012e52 220ad858d3
commit ee70fc26a5
8 changed files with 3798 additions and 1416 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
.mailmap
View File

@ -39,10 +39,11 @@ Julia Suvorova <jusual@mail.ru> Julia Suvorova via Qemu-devel <qemu-devel@nongnu
Justin Terry (VM) <juterry@microsoft.com> Justin Terry (VM) via Qemu-devel <qemu-devel@nongnu.org>
# Next, replace old addresses by a more recent one.
Anthony Liguori <anthony@codemonkey.ws> Anthony Liguori <aliguori@us.ibm.com>
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
Aleksandar Markovic <amarkovic@wavecomp.com> <aleksandar.markovic@mips.com>
Aleksandar Markovic <amarkovic@wavecomp.com> <aleksandar.markovic@imgtec.com>
Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> <arikalo@wavecomp.com>
Anthony Liguori <anthony@codemonkey.ws> Anthony Liguori <aliguori@us.ibm.com>
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
Paul Burton <pburton@wavecomp.com> <paul.burton@mips.com>
Paul Burton <pburton@wavecomp.com> <paul.burton@imgtec.com>
Paul Burton <pburton@wavecomp.com> <paul@archlinuxmips.org>

18
MAINTAINERS
View File

@ -208,7 +208,7 @@ F: disas/microblaze.c
MIPS TCG CPUs
M: Aurelien Jarno <aurelien@aurel32.net>
M: Aleksandar Markovic <amarkovic@wavecomp.com>
R: Aleksandar Rikalo <arikalo@wavecomp.com>
R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
S: Maintained
F: target/mips/
F: default-configs/*mips*
@ -363,7 +363,7 @@ F: target/arm/kvm.c
MIPS KVM CPUs
M: James Hogan <jhogan@kernel.org>
R: Aleksandar Rikalo <arikalo@wavecomp.com>
R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
S: Maintained
F: target/mips/kvm.c
@ -934,7 +934,7 @@ MIPS Machines
-------------
Jazz
M: Hervé Poussineau <hpoussin@reactos.org>
R: Aleksandar Rikalo <arikalo@wavecomp.com>
R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
S: Maintained
F: hw/mips/mips_jazz.c
F: hw/display/jazz_led.c
@ -942,7 +942,7 @@ F: hw/dma/rc4030.c
Malta
M: Aurelien Jarno <aurelien@aurel32.net>
R: Aleksandar Rikalo <arikalo@wavecomp.com>
R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
S: Maintained
F: hw/mips/mips_malta.c
F: hw/mips/gt64xxx_pci.c
@ -950,20 +950,20 @@ F: tests/acceptance/linux_ssh_mips_malta.py
Mipssim
M: Aleksandar Markovic <amarkovic@wavecomp.com>
R: Aleksandar Rikalo <arikalo@wavecomp.com>
R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
S: Odd Fixes
F: hw/mips/mips_mipssim.c
F: hw/net/mipsnet.c
R4000
M: Aurelien Jarno <aurelien@aurel32.net>
R: Aleksandar Rikalo <arikalo@wavecomp.com>
R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
S: Maintained
F: hw/mips/mips_r4k.c
Fulong 2E
M: Aleksandar Markovic <amarkovic@wavecomp.com>
R: Aleksandar Rikalo <arikalo@wavecomp.com>
R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
S: Odd Fixes
F: hw/mips/mips_fulong2e.c
F: hw/isa/vt82c686.c
@ -972,7 +972,7 @@ F: include/hw/isa/vt82c686.h
Boston
M: Paul Burton <pburton@wavecomp.com>
R: Aleksandar Rikalo <arikalo@wavecomp.com>
R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
S: Maintained
F: hw/core/loader-fit.c
F: hw/mips/boston.c
@ -2352,7 +2352,7 @@ F: disas/i386.c
MIPS TCG target
M: Aurelien Jarno <aurelien@aurel32.net>
R: Aleksandar Rikalo <arikalo@wavecomp.com>
R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
S: Maintained
F: tcg/mips/

123
target/mips/helper.c
View File

@ -39,8 +39,8 @@ enum {
#if !defined(CONFIG_USER_ONLY)
/* no MMU emulation */
int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
target_ulong address, int rw, int access_type)
int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
target_ulong address, int rw, int access_type)
{
*physical = address;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
@ -48,26 +48,28 @@ int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
}
/* fixed mapping MMU emulation */
int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
target_ulong address, int rw, int access_type)
int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
target_ulong address, int rw, int access_type)
{
if (address <= (int32_t)0x7FFFFFFFUL) {
if (!(env->CP0_Status & (1 << CP0St_ERL)))
if (!(env->CP0_Status & (1 << CP0St_ERL))) {
*physical = address + 0x40000000UL;
else
} else {
*physical = address;
} else if (address <= (int32_t)0xBFFFFFFFUL)
}
} else if (address <= (int32_t)0xBFFFFFFFUL) {
*physical = address & 0x1FFFFFFF;
else
} else {
*physical = address;
}
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TLBRET_MATCH;
}
/* MIPS32/MIPS64 R4000-style MMU emulation */
int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
target_ulong address, int rw, int access_type)
int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
target_ulong address, int rw, int access_type)
{
uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
int i;
@ -99,8 +101,9 @@ int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
*physical = tlb->PFN[n] | (address & (mask >> 1));
*prot = PAGE_READ;
if (n ? tlb->D1 : tlb->D0)
if (n ? tlb->D1 : tlb->D0) {
*prot |= PAGE_WRITE;
}
if (!(n ? tlb->XI1 : tlb->XI0)) {
*prot |= PAGE_EXEC;
}
@ -130,7 +133,7 @@ static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx)
int32_t adetlb_mask;
switch (mmu_idx) {
case 3 /* ERL */:
case 3: /* ERL */
/* If EU is set, always unmapped */
if (eu) {
return 0;
@ -204,7 +207,7 @@ static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical,
pa & ~(hwaddr)segmask);
}
static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
static int get_physical_address(CPUMIPSState *env, hwaddr *physical,
int *prot, target_ulong real_address,
int rw, int access_type, int mmu_idx)
{
@ -252,14 +255,15 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
} else {
segctl = env->CP0_SegCtl2 >> 16;
}
ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
access_type, mmu_idx, segctl,
0x3FFFFFFF);
ret = get_segctl_physical_address(env, physical, prot,
real_address, rw, access_type,
mmu_idx, segctl, 0x3FFFFFFF);
#if defined(TARGET_MIPS64)
} else if (address < 0x4000000000000000ULL) {
/* xuseg */
if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
ret = env->tlb->map_address(env, physical, prot,
real_address, rw, access_type);
} else {
ret = TLBRET_BADADDR;
}
@ -267,7 +271,8 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
/* xsseg */
if ((supervisor_mode || kernel_mode) &&
SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
ret = env->tlb->map_address(env, physical, prot,
real_address, rw, access_type);
} else {
ret = TLBRET_BADADDR;
}
@ -307,7 +312,8 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
/* xkseg */
if (kernel_mode && KX &&
address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
ret = env->tlb->map_address(env, physical, prot,
real_address, rw, access_type);
} else {
ret = TLBRET_BADADDR;
}
@ -328,8 +334,10 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
access_type, mmu_idx,
env->CP0_SegCtl0 >> 16, 0x1FFFFFFF);
} else {
/* kseg3 */
/* XXX: debug segment is not emulated */
/*
* kseg3
* XXX: debug segment is not emulated
*/
ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
access_type, mmu_idx,
env->CP0_SegCtl0, 0x1FFFFFFF);
@ -515,9 +523,9 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
#if defined(TARGET_MIPS64)
env->CP0_EntryHi &= env->SEGMask;
env->CP0_XContext =
/* PTEBase */ (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
/* R */ (extract64(address, 62, 2) << (env->SEGBITS - 9)) |
/* BadVPN2 */ (extract64(address, 13, env->SEGBITS - 13) << 4);
(env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | /* PTEBase */
(extract64(address, 62, 2) << (env->SEGBITS - 9)) | /* R */
(extract64(address, 13, env->SEGBITS - 13) << 4); /* BadVPN2 */
#endif
cs->exception_index = exception;
env->error_code = error_code;
@ -945,7 +953,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
}
#ifndef CONFIG_USER_ONLY
hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
int rw)
{
hwaddr physical;
int prot;
@ -1005,7 +1014,7 @@ static const char * const excp_names[EXCP_LAST + 1] = {
};
#endif
target_ulong exception_resume_pc (CPUMIPSState *env)
target_ulong exception_resume_pc(CPUMIPSState *env)
{
target_ulong bad_pc;
target_ulong isa_mode;
@ -1013,8 +1022,10 @@ target_ulong exception_resume_pc (CPUMIPSState *env)
isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
bad_pc = env->active_tc.PC | isa_mode;
if (env->hflags & MIPS_HFLAG_BMASK) {
/* If the exception was raised from a delay slot, come back to
the jump. */
/*
* If the exception was raised from a delay slot, come back to
* the jump.
*/
bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
}
@ -1022,14 +1033,14 @@ target_ulong exception_resume_pc (CPUMIPSState *env)
}
#if !defined(CONFIG_USER_ONLY)
static void set_hflags_for_handler (CPUMIPSState *env)
static void set_hflags_for_handler(CPUMIPSState *env)
{
/* Exception handlers are entered in 32-bit mode. */
env->hflags &= ~(MIPS_HFLAG_M16);
/* ...except that microMIPS lets you choose. */
if (env->insn_flags & ASE_MICROMIPS) {
env->hflags |= (!!(env->CP0_Config3
& (1 << CP0C3_ISA_ON_EXC))
env->hflags |= (!!(env->CP0_Config3 &
(1 << CP0C3_ISA_ON_EXC))
<< MIPS_HFLAG_M16_SHIFT);
}
}
@ -1096,10 +1107,12 @@ void mips_cpu_do_interrupt(CPUState *cs)
switch (cs->exception_index) {
case EXCP_DSS:
env->CP0_Debug |= 1 << CP0DB_DSS;
/* Debug single step cannot be raised inside a delay slot and
resume will always occur on the next instruction
(but we assume the pc has always been updated during
code translation). */
/*
* Debug single step cannot be raised inside a delay slot and
* resume will always occur on the next instruction
* (but we assume the pc has always been updated during
* code translation).
*/
env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
goto enter_debug_mode;
case EXCP_DINT:
@ -1111,7 +1124,8 @@ void mips_cpu_do_interrupt(CPUState *cs)
case EXCP_DBp:
env->CP0_Debug |= 1 << CP0DB_DBp;
/* Setup DExcCode - SDBBP instruction */
env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | 9 << CP0DB_DEC;
env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) |
(9 << CP0DB_DEC);
goto set_DEPC;
case EXCP_DDBS:
env->CP0_Debug |= 1 << CP0DB_DDBS;
@ -1132,8 +1146,9 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0;
env->hflags &= ~(MIPS_HFLAG_KSU);
/* EJTAG probe trap enable is not implemented... */
if (!(env->CP0_Status & (1 << CP0St_EXL)))
if (!(env->CP0_Status & (1 << CP0St_EXL))) {
env->CP0_Cause &= ~(1U << CP0Ca_BD);
}
env->active_tc.PC = env->exception_base + 0x480;
set_hflags_for_handler(env);
break;
@ -1159,8 +1174,9 @@ void mips_cpu_do_interrupt(CPUState *cs)
}
env->hflags |= MIPS_HFLAG_CP0;
env->hflags &= ~(MIPS_HFLAG_KSU);
if (!(env->CP0_Status & (1 << CP0St_EXL)))
if (!(env->CP0_Status & (1 << CP0St_EXL))) {
env->CP0_Cause &= ~(1U << CP0Ca_BD);
}
env->active_tc.PC = env->exception_base;
set_hflags_for_handler(env);
break;
@ -1176,12 +1192,16 @@ void mips_cpu_do_interrupt(CPUState *cs)
uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP;
if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
/* For VEIC mode, the external interrupt controller feeds
* the vector through the CP0Cause IP lines. */
/*
* For VEIC mode, the external interrupt controller feeds
* the vector through the CP0Cause IP lines.
*/
vector = pending;
} else {
/* Vectored Interrupts
* Mask with Status.IM7-IM0 to get enabled interrupts. */
/*
* Vectored Interrupts
* Mask with Status.IM7-IM0 to get enabled interrupts.
*/
pending &= (env->CP0_Status >> CP0St_IM) & 0xff;
/* Find the highest-priority interrupt. */
while (pending >>= 1) {
@ -1354,7 +1374,8 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->active_tc.PC += offset;
set_hflags_for_handler(env);
env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) |
(cause << CP0Ca_EC);
break;
default:
abort();
@ -1390,7 +1411,7 @@ bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
#if !defined(CONFIG_USER_ONLY)
void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
{
CPUState *cs = env_cpu(env);
r4k_tlb_t *tlb;
@ -1400,16 +1421,20 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
target_ulong mask;
tlb = &env->tlb->mmu.r4k.tlb[idx];
/* The qemu TLB is flushed when the ASID changes, so no need to
flush these entries again. */
/*
* The qemu TLB is flushed when the ASID changes, so no need to
* flush these entries again.
*/
if (tlb->G == 0 && tlb->ASID != ASID) {
return;
}
if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
/* For tlbwr, we can shadow the discarded entry into
a new (fake) TLB entry, as long as the guest can not
tell that it's there. */
/*
* For tlbwr, we can shadow the discarded entry into
* a new (fake) TLB entry, as long as the guest can not
* tell that it's there.
*/
env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
env->tlb->tlb_in_use++;
return;

155
target/mips/helper.h
View File

@ -822,6 +822,39 @@ DEF_HELPER_4(msa_bset_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_bset_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_bset_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_add_a_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_add_a_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_add_a_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_add_a_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_adds_a_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_adds_a_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_adds_a_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_adds_a_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_adds_s_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_adds_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_adds_s_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_adds_s_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_adds_u_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_adds_u_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_adds_u_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_adds_u_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_addv_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_addv_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_addv_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_addv_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_hadd_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_hadd_s_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_hadd_s_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_hadd_u_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_hadd_u_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_hadd_u_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ave_s_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ave_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ave_s_w, void, env, i32, i32, i32)
@ -877,6 +910,31 @@ DEF_HELPER_4(msa_div_u_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_div_u_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_div_u_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_max_a_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_max_a_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_max_a_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_max_a_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_max_s_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_max_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_max_s_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_max_s_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_max_u_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_max_u_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_max_u_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_max_u_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_min_a_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_min_a_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_min_a_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_min_a_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_min_s_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_min_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_min_s_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_min_s_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_min_u_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_min_u_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_min_u_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_min_u_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_mod_u_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_mod_u_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_mod_u_w, void, env, i32, i32, i32)
@ -887,11 +945,80 @@ DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_asub_s_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_asub_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_asub_s_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_asub_s_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_asub_u_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_asub_u_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_asub_u_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_asub_u_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_hsub_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_hsub_s_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_hsub_s_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_hsub_u_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_hsub_u_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_hsub_u_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvev_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvev_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvev_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvev_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvod_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvod_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvod_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvod_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvl_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvl_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvl_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvl_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvr_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvr_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvr_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvr_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32)
DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32)
DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32)
DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32)
DEF_HELPER_4(msa_pckev_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_pckev_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_pckev_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_pckev_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_pckod_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_pckod_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_pckod_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_pckod_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_sll_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_sll_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_sll_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_sll_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_sra_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_sra_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_sra_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_sra_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_srar_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_srar_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_srar_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_srar_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_srl_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_srl_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_srl_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_srl_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_srlr_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_srlr_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_srlr_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_srlr_d, void, env, i32, i32, i32)
DEF_HELPER_3(msa_move_v, void, env, i32, i32)
DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32)
@ -929,29 +1056,13 @@ DEF_HELPER_5(msa_sat_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srari_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_sll_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_sra_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srl_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_addv_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subv_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_max_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_max_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_min_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_min_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_max_a_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_min_a_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_add_a_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_adds_a_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_adds_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_adds_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subs_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subs_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subsus_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subsuu_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_asub_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_asub_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_mulv_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_maddv_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_msubv_df, void, env, i32, i32, i32, i32)
@ -963,19 +1074,7 @@ DEF_HELPER_5(msa_dpsub_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_dpsub_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_pckev_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_pckod_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_ilvl_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_ilvr_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_ilvev_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_ilvod_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srar_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srlr_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_hadd_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_hadd_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_hsub_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32)

3055
target/mips/msa_helper.c
View File

File diff suppressed because it is too large Load Diff

1010
target/mips/op_helper.c
View File

File diff suppressed because it is too large Load Diff

742
target/mips/translate.c
View File

@ -5546,78 +5546,181 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
gen_load_fpr64(ctx, t0, rs);
gen_load_fpr64(ctx, t1, rt);
#define LMI_HELPER(UP, LO) \
case OPC_##UP: gen_helper_##LO(t0, t0, t1); break
#define LMI_HELPER_1(UP, LO) \
case OPC_##UP: gen_helper_##LO(t0, t0); break
#define LMI_DIRECT(UP, LO, OP) \
case OPC_##UP: tcg_gen_##OP##_i64(t0, t0, t1); break
switch (opc) {
LMI_HELPER(PADDSH, paddsh);
LMI_HELPER(PADDUSH, paddush);
LMI_HELPER(PADDH, paddh);
LMI_HELPER(PADDW, paddw);
LMI_HELPER(PADDSB, paddsb);
LMI_HELPER(PADDUSB, paddusb);
LMI_HELPER(PADDB, paddb);
case OPC_PADDSH:
gen_helper_paddsh(t0, t0, t1);
break;
case OPC_PADDUSH:
gen_helper_paddush(t0, t0, t1);
break;
case OPC_PADDH:
gen_helper_paddh(t0, t0, t1);
break;
case OPC_PADDW:
gen_helper_paddw(t0, t0, t1);
break;
case OPC_PADDSB:
gen_helper_paddsb(t0, t0, t1);
break;
case OPC_PADDUSB:
gen_helper_paddusb(t0, t0, t1);
break;
case OPC_PADDB:
gen_helper_paddb(t0, t0, t1);
break;
LMI_HELPER(PSUBSH, psubsh);
LMI_HELPER(PSUBUSH, psubush);
LMI_HELPER(PSUBH, psubh);
LMI_HELPER(PSUBW, psubw);
LMI_HELPER(PSUBSB, psubsb);
LMI_HELPER(PSUBUSB, psubusb);
LMI_HELPER(PSUBB, psubb);
case OPC_PSUBSH:
gen_helper_psubsh(t0, t0, t1);
break;
case OPC_PSUBUSH:
gen_helper_psubush(t0, t0, t1);
break;
case OPC_PSUBH:
gen_helper_psubh(t0, t0, t1);
break;
case OPC_PSUBW:
gen_helper_psubw(t0, t0, t1);
break;
case OPC_PSUBSB:
gen_helper_psubsb(t0, t0, t1);
break;
case OPC_PSUBUSB:
gen_helper_psubusb(t0, t0, t1);
break;
case OPC_PSUBB:
gen_helper_psubb(t0, t0, t1);
break;
LMI_HELPER(PSHUFH, pshufh);
LMI_HELPER(PACKSSWH, packsswh);
LMI_HELPER(PACKSSHB, packsshb);
LMI_HELPER(PACKUSHB, packushb);
case OPC_PSHUFH:
gen_helper_pshufh(t0, t0, t1);
break;
case OPC_PACKSSWH:
gen_helper_packsswh(t0, t0, t1);
break;
case OPC_PACKSSHB:
gen_helper_packsshb(t0, t0, t1);
break;
case OPC_PACKUSHB:
gen_helper_packushb(t0, t0, t1);
break;
LMI_HELPER(PUNPCKLHW, punpcklhw);
LMI_HELPER(PUNPCKHHW, punpckhhw);
LMI_HELPER(PUNPCKLBH, punpcklbh);
LMI_HELPER(PUNPCKHBH, punpckhbh);
LMI_HELPER(PUNPCKLWD, punpcklwd);
LMI_HELPER(PUNPCKHWD, punpckhwd);
case OPC_PUNPCKLHW:
gen_helper_punpcklhw(t0, t0, t1);
break;
case OPC_PUNPCKHHW:
gen_helper_punpckhhw(t0, t0, t1);
break;
case OPC_PUNPCKLBH:
gen_helper_punpcklbh(t0, t0, t1);
break;
case OPC_PUNPCKHBH:
gen_helper_punpckhbh(t0, t0, t1);
break;
case OPC_PUNPCKLWD:
gen_helper_punpcklwd(t0, t0, t1);
break;
case OPC_PUNPCKHWD:
gen_helper_punpckhwd(t0, t0, t1);
break;
LMI_HELPER(PAVGH, pavgh);
LMI_HELPER(PAVGB, pavgb);
LMI_HELPER(PMAXSH, pmaxsh);
LMI_HELPER(PMINSH, pminsh);
LMI_HELPER(PMAXUB, pmaxub);
LMI_HELPER(PMINUB, pminub);
case OPC_PAVGH:
gen_helper_pavgh(t0, t0, t1);
break;
case OPC_PAVGB:
gen_helper_pavgb(t0, t0, t1);
break;
case OPC_PMAXSH:
gen_helper_pmaxsh(t0, t0, t1);
break;
case OPC_PMINSH:
gen_helper_pminsh(t0, t0, t1);
break;
case OPC_PMAXUB:
gen_helper_pmaxub(t0, t0, t1);
break;
case OPC_PMINUB:
gen_helper_pminub(t0, t0, t1);
break;
LMI_HELPER(PCMPEQW, pcmpeqw);
LMI_HELPER(PCMPGTW, pcmpgtw);
LMI_HELPER(PCMPEQH, pcmpeqh);
LMI_HELPER(PCMPGTH, pcmpgth);
LMI_HELPER(PCMPEQB, pcmpeqb);
LMI_HELPER(PCMPGTB, pcmpgtb);
case OPC_PCMPEQW:
gen_helper_pcmpeqw(t0, t0, t1);
break;
case OPC_PCMPGTW:
gen_helper_pcmpgtw(t0, t0, t1);
break;
case OPC_PCMPEQH:
gen_helper_pcmpeqh(t0, t0, t1);
break;
case OPC_PCMPGTH:
gen_helper_pcmpgth(t0, t0, t1);
break;
case OPC_PCMPEQB:
gen_helper_pcmpeqb(t0, t0, t1);
break;
case OPC_PCMPGTB:
gen_helper_pcmpgtb(t0, t0, t1);
break;
LMI_HELPER(PSLLW, psllw);
LMI_HELPER(PSLLH, psllh);
LMI_HELPER(PSRLW, psrlw);
LMI_HELPER(PSRLH, psrlh);
LMI_HELPER(PSRAW, psraw);
LMI_HELPER(PSRAH, psrah);
case OPC_PSLLW:
gen_helper_psllw(t0, t0, t1);
break;
case OPC_PSLLH:
gen_helper_psllh(t0, t0, t1);
break;
case OPC_PSRLW:
gen_helper_psrlw(t0, t0, t1);
break;
case OPC_PSRLH:
gen_helper_psrlh(t0, t0, t1);
break;
case OPC_PSRAW:
gen_helper_psraw(t0, t0, t1);
break;
case OPC_PSRAH:
gen_helper_psrah(t0, t0, t1);
break;
LMI_HELPER(PMULLH, pmullh);
LMI_HELPER(PMULHH, pmulhh);
LMI_HELPER(PMULHUH, pmulhuh);
LMI_HELPER(PMADDHW, pmaddhw);
case OPC_PMULLH:
gen_helper_pmullh(t0, t0, t1);
break;
case OPC_PMULHH:
gen_helper_pmulhh(t0, t0, t1);
break;
case OPC_PMULHUH:
gen_helper_pmulhuh(t0, t0, t1);
break;
case OPC_PMADDHW:
gen_helper_pmaddhw(t0, t0, t1);
break;
LMI_HELPER(PASUBUB, pasubub);
LMI_HELPER_1(BIADD, biadd);
LMI_HELPER_1(PMOVMSKB, pmovmskb);
case OPC_PASUBUB:
gen_helper_pasubub(t0, t0, t1);
break;
case OPC_BIADD:
gen_helper_biadd(t0, t0);
break;
case OPC_PMOVMSKB:
gen_helper_pmovmskb(t0, t0);
break;
LMI_DIRECT(PADDD, paddd, add);
LMI_DIRECT(PSUBD, psubd, sub);
LMI_DIRECT(XOR_CP2, xor, xor);
LMI_DIRECT(NOR_CP2, nor, nor);
LMI_DIRECT(AND_CP2, and, and);
LMI_DIRECT(OR_CP2, or, or);
case OPC_PADDD:
tcg_gen_add_i64(t0, t0, t1);
break;
case OPC_PSUBD:
tcg_gen_sub_i64(t0, t0, t1);
break;
case OPC_XOR_CP2:
tcg_gen_xor_i64(t0, t0, t1);
break;
case OPC_NOR_CP2:
tcg_gen_nor_i64(t0, t0, t1);
break;
case OPC_AND_CP2:
tcg_gen_and_i64(t0, t0, t1);
break;
case OPC_OR_CP2:
tcg_gen_or_i64(t0, t0, t1);
break;
case OPC_PANDN:
tcg_gen_andc_i64(t0, t1, t0);
@ -5770,9 +5873,6 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
return;
}
#undef LMI_HELPER
#undef LMI_DIRECT
gen_store_fpr64(ctx, t0, rd);
tcg_temp_free_i64(t0);
@ -28466,6 +28566,86 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
case OPC_ADD_A_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_add_a_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_add_a_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_add_a_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_add_a_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_ADDS_A_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_adds_a_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_adds_a_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_adds_a_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_adds_a_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_ADDS_S_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_adds_s_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_adds_s_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_adds_s_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_adds_s_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_ADDS_U_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_adds_u_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_adds_u_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_adds_u_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_adds_u_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_ADDV_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_addv_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_addv_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_addv_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_addv_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_AVE_S_df:
switch (df) {
case DF_BYTE:
@ -28642,6 +28822,102 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
case OPC_MAX_A_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_max_a_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_max_a_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_max_a_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_max_a_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_MAX_S_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_max_s_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_max_s_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_max_s_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_max_s_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_MAX_U_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_max_u_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_max_u_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_max_u_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_max_u_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_MIN_A_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_min_a_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_min_a_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_min_a_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_min_a_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_MIN_S_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_min_s_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_min_s_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_min_s_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_min_s_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_MIN_U_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_min_u_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_min_u_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_min_u_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_min_u_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_MOD_S_df:
switch (df) {
case DF_BYTE:
@ -28674,14 +28950,213 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
case OPC_ASUB_S_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_asub_s_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_asub_s_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_asub_s_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_asub_s_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_ASUB_U_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_asub_u_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_asub_u_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_asub_u_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_asub_u_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_ILVEV_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_ilvev_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_ilvev_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_ilvev_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_ilvev_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_ILVOD_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_ilvod_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_ilvod_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_ilvod_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_ilvod_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_ILVL_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_ilvl_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_ilvl_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_ilvl_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_ilvl_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_ILVR_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_ilvr_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_ilvr_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_ilvr_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_ilvr_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_PCKEV_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_pckev_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_pckev_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_pckev_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_pckev_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_PCKOD_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_pckod_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_pckod_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_pckod_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_pckod_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_SLL_df:
gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt);
switch (df) {
case DF_BYTE:
gen_helper_msa_sll_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_sll_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_sll_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_sll_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_ADDV_df:
gen_helper_msa_addv_df(cpu_env, tdf, twd, tws, twt);
case OPC_SRA_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_sra_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_sra_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_sra_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_sra_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_ADD_A_df:
gen_helper_msa_add_a_df(cpu_env, tdf, twd, tws, twt);
case OPC_SRAR_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_srar_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_srar_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_srar_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_srar_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_SRL_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_srl_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_srl_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_srl_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_srl_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_SRLR_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_srlr_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_srlr_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_srlr_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_srlr_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_SUBS_S_df:
gen_helper_msa_subs_s_df(cpu_env, tdf, twd, tws, twt);
@ -28695,15 +29170,9 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_VSHF_df:
gen_helper_msa_vshf_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_SRA_df:
gen_helper_msa_sra_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_SUBV_df:
gen_helper_msa_subv_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_ADDS_A_df:
gen_helper_msa_adds_a_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_SUBS_U_df:
gen_helper_msa_subs_u_df(cpu_env, tdf, twd, tws, twt);
break;
@ -28713,72 +29182,15 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_SPLAT_df:
gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_SRAR_df:
gen_helper_msa_srar_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_SRL_df:
gen_helper_msa_srl_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_MAX_S_df:
gen_helper_msa_max_s_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_ADDS_S_df:
gen_helper_msa_adds_s_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_SUBSUS_U_df:
gen_helper_msa_subsus_u_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_MSUBV_df:
gen_helper_msa_msubv_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_PCKEV_df:
gen_helper_msa_pckev_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_SRLR_df:
gen_helper_msa_srlr_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_MAX_U_df:
gen_helper_msa_max_u_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_ADDS_U_df:
gen_helper_msa_adds_u_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_SUBSUU_S_df:
gen_helper_msa_subsuu_s_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_PCKOD_df:
gen_helper_msa_pckod_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_MIN_S_df:
gen_helper_msa_min_s_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_ASUB_S_df:
gen_helper_msa_asub_s_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_ILVL_df:
gen_helper_msa_ilvl_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_MIN_U_df:
gen_helper_msa_min_u_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_ASUB_U_df:
gen_helper_msa_asub_u_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_ILVR_df:
gen_helper_msa_ilvr_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_MAX_A_df:
gen_helper_msa_max_a_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_ILVEV_df:
gen_helper_msa_ilvev_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_MIN_A_df:
gen_helper_msa_min_a_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_ILVOD_df:
gen_helper_msa_ilvod_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_DOTP_S_df:
case OPC_DOTP_U_df:
@ -28795,6 +29207,58 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
break;
}
switch (MASK_MSA_3R(ctx->opcode)) {
case OPC_HADD_S_df:
switch (df) {
case DF_HALF:
gen_helper_msa_hadd_s_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_hadd_s_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_hadd_s_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_HADD_U_df:
switch (df) {
case DF_HALF:
gen_helper_msa_hadd_u_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_hadd_u_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_hadd_u_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_HSUB_S_df:
switch (df) {
case DF_HALF:
gen_helper_msa_hsub_s_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_hsub_s_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_hsub_s_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_HSUB_U_df:
switch (df) {
case DF_HALF:
gen_helper_msa_hsub_u_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_hsub_u_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_hsub_u_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_DOTP_S_df:
gen_helper_msa_dotp_s_df(cpu_env, tdf, twd, tws, twt);
break;
@ -28810,21 +29274,9 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_DPSUB_S_df:
gen_helper_msa_dpsub_s_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_HADD_S_df:
gen_helper_msa_hadd_s_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_DPSUB_U_df:
gen_helper_msa_dpsub_u_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_HADD_U_df:
gen_helper_msa_hadd_u_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_HSUB_S_df:
gen_helper_msa_hsub_s_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_HSUB_U_df:
gen_helper_msa_hsub_u_df(cpu_env, tdf, twd, tws, twt);
break;
}
break;
default:

106
tests/acceptance/linux_ssh_mips_malta.py
View File

@ -25,15 +25,44 @@ class LinuxSSH(Test):
KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 '
VM_IP = '127.0.0.1'
BASE_URL = 'https://people.debian.org/~aurel32/qemu/'
IMAGE_INFO = {
'be': {'image_url': ('https://people.debian.org/~aurel32/qemu/mips/'
'debian_wheezy_mips_standard.qcow2'),
'image_hash': '8987a63270df67345b2135a6b7a4885a35e392d5'},
'le': {'image_url': ('https://people.debian.org/~aurel32/qemu/mipsel/'
'debian_wheezy_mipsel_standard.qcow2'),
'image_hash': '7866764d9de3ef536ffca24c9fb9f04ffdb45802'}
'be': {'base_url': 'mips',
'image_name': 'debian_wheezy_mips_standard.qcow2',
'image_hash': '8987a63270df67345b2135a6b7a4885a35e392d5',
'kernel_hash': {
32: '592e384a4edc16dade52a6cd5c785c637bcbc9ad',
64: 'db6eea7de35d36c77d8c165b6bcb222e16eb91db'}
},
'le': {'base_url': 'mipsel',
'image_name': 'debian_wheezy_mipsel_standard.qcow2',
'image_hash': '7866764d9de3ef536ffca24c9fb9f04ffdb45802',
'kernel_hash': {
32: 'a66bea5a8adaa2cb3d36a1d4e0ccdb01be8f6c2a',
64: '6a7f77245acf231415a0e8b725d91ed2f3487794'}
}
}
CPU_INFO = {
32: {'cpu': 'MIPS 24Kc', 'kernel_release': '3.2.0-4-4kc-malta'},
64: {'cpu': 'MIPS 20Kc', 'kernel_release': '3.2.0-4-5kc-malta'}
}
def get_url(self, endianess, path=''):
qkey = {'le': 'el', 'be': ''}
return '%s/mips%s/%s' % (self.BASE_URL, qkey[endianess], path)
def get_image_info(self, endianess):
dinfo = self.IMAGE_INFO[endianess]
image_url = self.get_url(endianess, dinfo['image_name'])
image_hash = dinfo['image_hash']
return (image_url, image_hash)
def get_kernel_info(self, endianess, wordsize):
minfo = self.CPU_INFO[wordsize]
kernel_url = self.get_url(endianess,
'vmlinux-%s' % minfo['kernel_release'])
kernel_hash = self.IMAGE_INFO[endianess]['kernel_hash'][wordsize]
return kernel_url, kernel_hash
@skipUnless(ssh.SSH_CLIENT_BINARY, 'No SSH client available')
@skipUnless(os.getenv('AVOCADO_TIMEOUT_EXPECTED'), 'Test might timeout')
@ -91,8 +120,7 @@ class LinuxSSH(Test):
return stdout_lines, stderr_lines
def boot_debian_wheezy_image_and_ssh_login(self, endianess, kernel_path):
image_url = self.IMAGE_INFO[endianess]['image_url']
image_hash = self.IMAGE_INFO[endianess]['image_hash']
image_url, image_hash = self.get_image_info(endianess)
image_path = self.fetch_asset(image_url, asset_hash=image_hash)
self.vm.set_machine('malta')
@ -102,7 +130,7 @@ class LinuxSSH(Test):
self.vm.add_args('-no-reboot',
'-kernel', kernel_path,
'-append', kernel_command_line,
'-hda', image_path,
'-drive', 'file=%s,snapshot=on' % image_path,
'-netdev', 'user,id=vnet,hostfwd=:127.0.0.1:0-:22',
'-device', 'pcnet,netdev=vnet')
self.vm.launch()
@ -127,34 +155,31 @@ class LinuxSSH(Test):
else:
self.fail('"%s" output does not contain "%s"' % (cmd, exp))
def run_common_commands(self):
def run_common_commands(self, wordsize):
self.ssh_command_output_contains(
'cat /proc/cpuinfo',
'24Kc')
self.CPU_INFO[wordsize]['cpu'])
self.ssh_command_output_contains(
'uname -m',
'mips')
self.ssh_command_output_contains(
'uname -r',
'3.2.0-4-4kc-malta')
self.CPU_INFO[wordsize]['kernel_release'])
self.ssh_command_output_contains(
'cat /proc/interrupts',
'timer')
'XT-PIC timer')
self.ssh_command_output_contains(
'cat /proc/interrupts',
'i8042')
'XT-PIC i8042')
self.ssh_command_output_contains(
'cat /proc/interrupts',
'serial')
'XT-PIC serial')
self.ssh_command_output_contains(
'cat /proc/interrupts',
'ata_piix')
'XT-PIC ata_piix')
self.ssh_command_output_contains(
'cat /proc/interrupts',
'eth0')
self.ssh_command_output_contains(
'cat /proc/interrupts',
'eth0')
'XT-PIC eth0')
self.ssh_command_output_contains(
'cat /proc/devices',
'input')
@ -166,13 +191,13 @@ class LinuxSSH(Test):
'fb')
self.ssh_command_output_contains(
'cat /proc/ioports',
'serial')
' : serial')
self.ssh_command_output_contains(
'cat /proc/ioports',
'ata_piix')
' : ata_piix')
self.ssh_command_output_contains(
'cat /proc/ioports',
'piix4_smbus')
' : piix4_smbus')
self.ssh_command_output_contains(
'lspci -d 11ab:4620',
'GT-64120')
@ -182,18 +207,21 @@ class LinuxSSH(Test):
self.ssh_command_output_contains(
'cat /proc/mtd',
'YAMON')
# Empty 'Board Config'
# Empty 'Board Config' (64KB)
self.ssh_command_output_contains(
'md5sum /dev/mtd2ro',
'0dfbe8aa4c20b52e1b8bf3cb6cbdf193')
def check_mips_malta(self, endianess, kernel_path, uname_m):
def check_mips_malta(self, uname_m, endianess):
wordsize = 64 if '64' in uname_m else 32
kernel_url, kernel_hash = self.get_kernel_info(endianess, wordsize)
kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
self.boot_debian_wheezy_image_and_ssh_login(endianess, kernel_path)
stdout, _ = self.ssh_command('uname -a')
self.assertIn(True, [uname_m + " GNU/Linux" in line for line in stdout])
self.run_common_commands()
self.run_common_commands(wordsize)
self.shutdown_via_ssh()
def test_mips_malta32eb_kernel3_2_0(self):
@ -203,12 +231,7 @@ class LinuxSSH(Test):
:avocado: tags=endian:big
:avocado: tags=device:pcnet32
"""
kernel_url = ('https://people.debian.org/~aurel32/qemu/mips/'
'vmlinux-3.2.0-4-4kc-malta')
kernel_hash = '592e384a4edc16dade52a6cd5c785c637bcbc9ad'
kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
self.check_mips_malta('be', kernel_path, 'mips')
self.check_mips_malta('mips', 'be')
def test_mips_malta32el_kernel3_2_0(self):
"""
@ -217,12 +240,7 @@ class LinuxSSH(Test):
:avocado: tags=endian:little
:avocado: tags=device:pcnet32
"""
kernel_url = ('https://people.debian.org/~aurel32/qemu/mipsel/'
'vmlinux-3.2.0-4-4kc-malta')
kernel_hash = 'a66bea5a8adaa2cb3d36a1d4e0ccdb01be8f6c2a'
kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
self.check_mips_malta('le', kernel_path, 'mips')
self.check_mips_malta('mips', 'le')
def test_mips_malta64eb_kernel3_2_0(self):
"""
@ -231,11 +249,7 @@ class LinuxSSH(Test):
:avocado: tags=endian:big
:avocado: tags=device:pcnet32
"""
kernel_url = ('https://people.debian.org/~aurel32/qemu/mips/'
'vmlinux-3.2.0-4-5kc-malta')
kernel_hash = 'db6eea7de35d36c77d8c165b6bcb222e16eb91db'
kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
self.check_mips_malta('be', kernel_path, 'mips64')
self.check_mips_malta('mips64', 'be')
def test_mips_malta64el_kernel3_2_0(self):
"""
@ -244,8 +258,4 @@ class LinuxSSH(Test):
:avocado: tags=endian:little
:avocado: tags=device:pcnet32
"""
kernel_url = ('https://people.debian.org/~aurel32/qemu/mipsel/'
'vmlinux-3.2.0-4-5kc-malta')
kernel_hash = '6a7f77245acf231415a0e8b725d91ed2f3487794'
kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
self.check_mips_malta('le', kernel_path, 'mips64')
self.check_mips_malta('mips64', 'le')