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microblaze hw/: Don't use CPUState 

Scripted conversion:
  for file in hw/microblaze_*.[hc] hw/petalogix_ml605_mmu.c hw/petalogix_s3adsp1800_mmu.c; do
    sed -i "s/CPUState/CPUMBState/g" $file
  done

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Andreas Färber 2012-03-14 01:38:23 +01:00
parent 7927df3a8b
commit ee11850732
6 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
hw/microblaze_boot.c
View File

@ -35,7 +35,7 @@
static struct static struct
{ {
void (*machine_cpu_reset)(CPUState *); void (*machine_cpu_reset)(CPUMBState *);
uint32_t bootstrap_pc; uint32_t bootstrap_pc;
uint32_t cmdline; uint32_t cmdline;
uint32_t fdt; uint32_t fdt;
@ -43,7 +43,7 @@ static struct
static void main_cpu_reset(void *opaque) static void main_cpu_reset(void *opaque)
{ {
CPUState *env = opaque; CPUMBState *env = opaque;
cpu_state_reset(env); cpu_state_reset(env);
env->regs[5] = boot_info.cmdline; env->regs[5] = boot_info.cmdline;
@ -99,9 +99,9 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
return addr - 0x30000000LL; return addr - 0x30000000LL;
} }
void microblaze_load_kernel(CPUState *env, target_phys_addr_t ddr_base, void microblaze_load_kernel(CPUMBState *env, target_phys_addr_t ddr_base,
uint32_t ramsize, const char *dtb_filename, uint32_t ramsize, const char *dtb_filename,
void (*machine_cpu_reset)(CPUState *)) void (*machine_cpu_reset)(CPUMBState *))
{ {
QemuOpts *machine_opts; QemuOpts *machine_opts;

4
hw/microblaze_boot.h
View File

@ -3,8 +3,8 @@
#include "hw.h" #include "hw.h"
void microblaze_load_kernel(CPUState *env, target_phys_addr_t ddr_base, void microblaze_load_kernel(CPUMBState *env, target_phys_addr_t ddr_base,
uint32_t ramsize, const char *dtb_filename, uint32_t ramsize, const char *dtb_filename,
void (*machine_cpu_reset)(CPUState *)); void (*machine_cpu_reset)(CPUMBState *));
#endif /* __MICROBLAZE_BOOT __ */ #endif /* __MICROBLAZE_BOOT __ */

4
hw/microblaze_pic_cpu.c
View File

@ -29,7 +29,7 @@
static void microblaze_pic_cpu_handler(void *opaque, int irq, int level) static void microblaze_pic_cpu_handler(void *opaque, int irq, int level)
{ {
CPUState *env = (CPUState *)opaque; CPUMBState *env = (CPUMBState *)opaque;
int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD; int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
if (level) if (level)
@ -38,7 +38,7 @@ static void microblaze_pic_cpu_handler(void *opaque, int irq, int level)
cpu_reset_interrupt(env, type); cpu_reset_interrupt(env, type);
} }
qemu_irq *microblaze_pic_init_cpu(CPUState *env) qemu_irq *microblaze_pic_init_cpu(CPUMBState *env)
{ {
return qemu_allocate_irqs(microblaze_pic_cpu_handler, env, 2); return qemu_allocate_irqs(microblaze_pic_cpu_handler, env, 2);
} }

2
hw/microblaze_pic_cpu.h
View File

@ -3,6 +3,6 @@
#include "qemu-common.h" #include "qemu-common.h"
qemu_irq *microblaze_pic_init_cpu(CPUState *env); qemu_irq *microblaze_pic_init_cpu(CPUMBState *env);
#endif /* MICROBLAZE_PIC_CPU_H */ #endif /* MICROBLAZE_PIC_CPU_H */

4
hw/petalogix_ml605_mmu.c
View File

@ -54,7 +54,7 @@
#define AXIENET_BASEADDR 0x82780000 #define AXIENET_BASEADDR 0x82780000
#define AXIDMA_BASEADDR 0x84600000 #define AXIDMA_BASEADDR 0x84600000
static void machine_cpu_reset(CPUState *env) static void machine_cpu_reset(CPUMBState *env)
{ {
env->pvr.regs[10] = 0x0e000000; /* virtex 6 */ env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
/* setup pvr to match kernel setting */ /* setup pvr to match kernel setting */
@ -75,7 +75,7 @@ petalogix_ml605_init(ram_addr_t ram_size,
{ {
MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *address_space_mem = get_system_memory();
DeviceState *dev; DeviceState *dev;
CPUState *env; CPUMBState *env;
DriveInfo *dinfo; DriveInfo *dinfo;
int i; int i;
target_phys_addr_t ddr_base = MEMORY_BASEADDR; target_phys_addr_t ddr_base = MEMORY_BASEADDR;

4
hw/petalogix_s3adsp1800_mmu.c
View File

@ -49,7 +49,7 @@
#define UARTLITE_BASEADDR 0x84000000 #define UARTLITE_BASEADDR 0x84000000
#define ETHLITE_BASEADDR 0x81000000 #define ETHLITE_BASEADDR 0x81000000
static void machine_cpu_reset(CPUState *env) static void machine_cpu_reset(CPUMBState *env)
{ {
/* FIXME: move to machine specfic cpu reset */ /* FIXME: move to machine specfic cpu reset */
env->pvr.regs[10] = 0x0c000000; /* spartan 3a dsp family. */ env->pvr.regs[10] = 0x0c000000; /* spartan 3a dsp family. */
@ -63,7 +63,7 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model) const char *initrd_filename, const char *cpu_model)
{ {
DeviceState *dev; DeviceState *dev;
CPUState *env; CPUMBState *env;
DriveInfo *dinfo; DriveInfo *dinfo;
int i; int i;
target_phys_addr_t ddr_base = MEMORY_BASEADDR; target_phys_addr_t ddr_base = MEMORY_BASEADDR;