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target/riscv: Update CSR bits name for svadu extension 

The Svadu specification updated the name of the *envcfg bit from
HADE to ADUE.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230816141916.66898-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li 2023-08-16 22:19:16 +08:00 committed by Alistair Francis
parent 9ff3140631
commit ed67d63798
4 changed files with 15 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
target/riscv/cpu.c
View File

@ -886,9 +886,9 @@ static void riscv_cpu_reset_hold(Object *obj)
env->two_stage_lookup = false; env->two_stage_lookup = false;
env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) |
(cpu->cfg.ext_svadu ? MENVCFG_HADE : 0); (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0);
env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) |
(cpu->cfg.ext_svadu ? HENVCFG_HADE : 0); (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0);
/* Initialized default priorities of local interrupts. */ /* Initialized default priorities of local interrupts. */
for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {

8
target/riscv/cpu_bits.h
View File

@ -745,12 +745,12 @@ typedef enum RISCVException {
#define MENVCFG_CBIE (3UL << 4) #define MENVCFG_CBIE (3UL << 4)
#define MENVCFG_CBCFE BIT(6) #define MENVCFG_CBCFE BIT(6)
#define MENVCFG_CBZE BIT(7) #define MENVCFG_CBZE BIT(7)
#define MENVCFG_HADE (1ULL << 61) #define MENVCFG_ADUE (1ULL << 61)
#define MENVCFG_PBMTE (1ULL << 62) #define MENVCFG_PBMTE (1ULL << 62)
#define MENVCFG_STCE (1ULL << 63) #define MENVCFG_STCE (1ULL << 63)
/* For RV32 */ /* For RV32 */
#define MENVCFGH_HADE BIT(29) #define MENVCFGH_ADUE BIT(29)
#define MENVCFGH_PBMTE BIT(30) #define MENVCFGH_PBMTE BIT(30)
#define MENVCFGH_STCE BIT(31) #define MENVCFGH_STCE BIT(31)
@ -763,12 +763,12 @@ typedef enum RISCVException {
#define HENVCFG_CBIE MENVCFG_CBIE #define HENVCFG_CBIE MENVCFG_CBIE
#define HENVCFG_CBCFE MENVCFG_CBCFE #define HENVCFG_CBCFE MENVCFG_CBCFE
#define HENVCFG_CBZE MENVCFG_CBZE #define HENVCFG_CBZE MENVCFG_CBZE
#define HENVCFG_HADE MENVCFG_HADE #define HENVCFG_ADUE MENVCFG_ADUE
#define HENVCFG_PBMTE MENVCFG_PBMTE #define HENVCFG_PBMTE MENVCFG_PBMTE
#define HENVCFG_STCE MENVCFG_STCE #define HENVCFG_STCE MENVCFG_STCE
/* For RV32 */ /* For RV32 */
#define HENVCFGH_HADE MENVCFGH_HADE #define HENVCFGH_ADUE MENVCFGH_ADUE
#define HENVCFGH_PBMTE MENVCFGH_PBMTE #define HENVCFGH_PBMTE MENVCFGH_PBMTE
#define HENVCFGH_STCE MENVCFGH_STCE #define HENVCFGH_STCE MENVCFGH_STCE

6
target/riscv/cpu_helper.c
View File

@ -861,11 +861,11 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
} }
bool pbmte = env->menvcfg & MENVCFG_PBMTE; bool pbmte = env->menvcfg & MENVCFG_PBMTE;
bool hade = env->menvcfg & MENVCFG_HADE; bool adue = env->menvcfg & MENVCFG_ADUE;
if (first_stage && two_stage && env->virt_enabled) { if (first_stage && two_stage && env->virt_enabled) {
pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
hade = hade && (env->henvcfg & HENVCFG_HADE); adue = adue && (env->henvcfg & HENVCFG_ADUE);
} }
int ptshift = (levels - 1) * ptidxbits; int ptshift = (levels - 1) * ptidxbits;
@ -1026,7 +1026,7 @@ restart:
/* Page table updates need to be atomic with MTTCG enabled */ /* Page table updates need to be atomic with MTTCG enabled */
if (updated_pte != pte && !is_debug) { if (updated_pte != pte && !is_debug) {
if (!hade) { if (!adue) {
return TRANSLATE_FAIL; return TRANSLATE_FAIL;
} }

12
target/riscv/csr.c
View File

@ -1957,7 +1957,7 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
if (riscv_cpu_mxl(env) == MXL_RV64) { if (riscv_cpu_mxl(env) == MXL_RV64) {
mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
(cfg->ext_sstc ? MENVCFG_STCE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) |
(cfg->ext_svadu ? MENVCFG_HADE : 0); (cfg->ext_svadu ? MENVCFG_ADUE : 0);
} }
env->menvcfg = (env->menvcfg & ~mask) | (val & mask); env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
@ -1977,7 +1977,7 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
(cfg->ext_sstc ? MENVCFG_STCE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) |
(cfg->ext_svadu ? MENVCFG_HADE : 0); (cfg->ext_svadu ? MENVCFG_ADUE : 0);
uint64_t valh = (uint64_t)val << 32; uint64_t valh = (uint64_t)val << 32;
env->menvcfg = (env->menvcfg & ~mask) | (valh & mask); env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
@ -2029,7 +2029,7 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
* henvcfg.stce is read_only 0 when menvcfg.stce = 0 * henvcfg.stce is read_only 0 when menvcfg.stce = 0
* henvcfg.hade is read_only 0 when menvcfg.hade = 0 * henvcfg.hade is read_only 0 when menvcfg.hade = 0
*/ */
*val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) | *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) |
env->menvcfg); env->menvcfg);
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} }
@ -2046,7 +2046,7 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
} }
if (riscv_cpu_mxl(env) == MXL_RV64) { if (riscv_cpu_mxl(env) == MXL_RV64) {
mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE); mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE);
} }
env->henvcfg = (env->henvcfg & ~mask) | (val & mask); env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
@ -2064,7 +2064,7 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
return ret; return ret;
} }
*val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) | *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) |
env->menvcfg)) >> 32; env->menvcfg)) >> 32;
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} }
@ -2073,7 +2073,7 @@ static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
target_ulong val) target_ulong val)
{ {
uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE |
HENVCFG_HADE); HENVCFG_ADUE);
uint64_t valh = (uint64_t)val << 32; uint64_t valh = (uint64_t)val << 32;
RISCVException ret; RISCVException ret;