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target/arm: Create new arm_v7m_mmu_idx_for_secstate_and_priv() 

The TT instruction is going to need to look up the MMU index
for a specified security and privilege state. Refactor the
existing arm_v7m_mmu_idx_for_secstate() into a version that
lets you specify the privilege state and one that uses the
current state of the CPU.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1512153879-5291-6-git-send-email-peter.maydell@linaro.org
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Peter Maydell 2017-12-13 17:59:23 +00:00
parent 62593718d7
commit ec8e334028
1 changed files with 16 additions and 5 deletions
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21
target/arm/cpu.h
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@ -2339,14 +2339,16 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
} }
} }
/* Return the MMU index for a v7M CPU in the specified security state */ /* Return the MMU index for a v7M CPU in the specified security and
static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, * privilege state
bool secstate) */
static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
bool secstate,
bool priv)
{ {
int el = arm_current_el(env);
ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
if (el != 0) { if (priv) {
mmu_idx |= ARM_MMU_IDX_M_PRIV; mmu_idx |= ARM_MMU_IDX_M_PRIV;
} }
@ -2361,6 +2363,15 @@ static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env,
return mmu_idx; return mmu_idx;
} }
/* Return the MMU index for a v7M CPU in the specified security state */
static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env,
bool secstate)
{
bool priv = arm_current_el(env) != 0;
return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
}
/* Determine the current mmu_idx to use for normal loads/stores */ /* Determine the current mmu_idx to use for normal loads/stores */
static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
{ {