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target/riscv: check before allocating TCG temps 

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200626205917.4545-5-zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200724002807.441147-8-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
LIU Zhiwei 2020-07-23 17:28:07 -07:00 committed by Alistair Francis
parent 6e0229e638
commit ec80f87459
2 changed files with 8 additions and 8 deletions
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8
target/riscv/insn_trans/trans_rvd.c.inc
View File

@ -20,10 +20,10 @@
static bool trans_fld(DisasContext *ctx, arg_fld *a) static bool trans_fld(DisasContext *ctx, arg_fld *a)
{ {
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
REQUIRE_FPU; REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD); REQUIRE_EXT(ctx, RVD);
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm); tcg_gen_addi_tl(t0, t0, a->imm);
tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ); tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
@ -35,10 +35,10 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
static bool trans_fsd(DisasContext *ctx, arg_fsd *a) static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
{ {
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
REQUIRE_FPU; REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD); REQUIRE_EXT(ctx, RVD);
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm); tcg_gen_addi_tl(t0, t0, a->imm);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);

8
target/riscv/insn_trans/trans_rvf.c.inc
View File

@ -25,10 +25,10 @@
static bool trans_flw(DisasContext *ctx, arg_flw *a) static bool trans_flw(DisasContext *ctx, arg_flw *a)
{ {
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
REQUIRE_FPU; REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF); REQUIRE_EXT(ctx, RVF);
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm); tcg_gen_addi_tl(t0, t0, a->imm);
tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL); tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
@ -41,11 +41,11 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
static bool trans_fsw(DisasContext *ctx, arg_fsw *a) static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
{ {
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGv t0 = tcg_temp_new(); TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1); gen_get_gpr(t0, a->rs1);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
tcg_gen_addi_tl(t0, t0, a->imm); tcg_gen_addi_tl(t0, t0, a->imm);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);