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target/ppc: Implemented XXSPLTIW using decodetree
Implemented the XXSPLTIW instruction, using decodetree. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211104123719.323713-22-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -39,6 +39,10 @@
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@8RR_D_IX ...... .. .... .. .. ................ \
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...... ..... ... ix:1 . ................ \
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&8RR_D_IX si=%8rr_si xt=%8rr_xt
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&8RR_D xt si:int32_t
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@8RR_D ...... .. .... .. .. ................ \
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...... ..... .... . ................ \
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&8RR_D si=%8rr_si xt=%8rr_xt
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### Fixed-Point Load Instructions
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@ -165,5 +169,7 @@ PLXVP 000001 00 0--.-- .................. \
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PSTXVP 000001 00 0--.-- .................. \
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111110 ..... ..... ................ @8LS_D_TSXP
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XXSPLTIW 000001 01 0000 -- -- ................ \
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100000 ..... 0011 . ................ @8RR_D
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XXSPLTI32DX 000001 01 0000 -- -- ................ \
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100000 ..... 000 .. ................ @8RR_D_IX
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@ -1466,6 +1466,16 @@ static bool trans_XXSPLTIB(DisasContext *ctx, arg_X_imm8 *a)
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return true;
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}
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static bool trans_XXSPLTIW(DisasContext *ctx, arg_8RR_D *a)
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{
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REQUIRE_INSNS_FLAGS2(ctx, ISA310);
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REQUIRE_VSX(ctx);
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tcg_gen_gvec_dup_imm(MO_32, vsr_full_offset(a->xt), 16, 16, a->si);
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return true;
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}
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static bool trans_XXSPLTI32DX(DisasContext *ctx, arg_8RR_D_IX *a)
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{
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TCGv_i32 imm;
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