mirror of https://github.com/xemu-project/xemu.git
hw/arm/smmu: Introduce smmu_iotlb_inv_asid_vmid
Soon, Instead of doing TLB invalidation by ASID only, VMID will be also required. Add smmu_iotlb_inv_asid_vmid() which invalidates by both ASID and VMID. However, at the moment this function is only used in SMMU_CMD_TLBI_NH_ASID which is a stage-1 command, so passing VMID = -1 keeps the original behaviour. Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Mostafa Saleh <smostafa@google.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20240715084519.1189624-14-smostafa@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -159,13 +159,14 @@ void smmu_iotlb_inv_all(SMMUState *s)
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g_hash_table_remove_all(s->iotlb);
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}
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static gboolean smmu_hash_remove_by_asid(gpointer key, gpointer value,
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gpointer user_data)
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static gboolean smmu_hash_remove_by_asid_vmid(gpointer key, gpointer value,
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gpointer user_data)
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{
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int asid = *(int *)user_data;
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SMMUIOTLBPageInvInfo *info = (SMMUIOTLBPageInvInfo *)user_data;
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SMMUIOTLBKey *iotlb_key = (SMMUIOTLBKey *)key;
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return SMMU_IOTLB_ASID(*iotlb_key) == asid;
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return (SMMU_IOTLB_ASID(*iotlb_key) == info->asid) &&
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(SMMU_IOTLB_VMID(*iotlb_key) == info->vmid);
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}
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static gboolean smmu_hash_remove_by_vmid(gpointer key, gpointer value,
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@ -270,10 +271,15 @@ void smmu_iotlb_inv_ipa(SMMUState *s, int vmid, dma_addr_t ipa, uint8_t tg,
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&info);
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}
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void smmu_iotlb_inv_asid(SMMUState *s, int asid)
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void smmu_iotlb_inv_asid_vmid(SMMUState *s, int asid, int vmid)
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{
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trace_smmu_iotlb_inv_asid(asid);
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g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid, &asid);
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SMMUIOTLBPageInvInfo info = {
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.asid = asid,
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.vmid = vmid,
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};
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trace_smmu_iotlb_inv_asid_vmid(asid, vmid);
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g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid_vmid, &info);
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}
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void smmu_iotlb_inv_vmid(SMMUState *s, int vmid)
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@ -1357,7 +1357,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
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trace_smmuv3_cmdq_tlbi_nh_asid(asid);
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smmu_inv_notifiers_all(&s->smmu_state);
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smmu_iotlb_inv_asid(bs, asid);
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smmu_iotlb_inv_asid_vmid(bs, asid, -1);
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break;
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}
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case SMMU_CMD_TLBI_NH_ALL:
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@ -11,7 +11,7 @@ smmu_ptw_page_pte(int stage, int level, uint64_t iova, uint64_t baseaddr, uint6
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smmu_ptw_block_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t iova, uint64_t gpa, int bsize_mb) "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" iova=0x%"PRIx64" block address = 0x%"PRIx64" block size = %d MiB"
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smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr, uint64_t pte) "baseaddr=0x%"PRIx64" index=0x%x, pteaddr=0x%"PRIx64", pte=0x%"PRIx64
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smmu_iotlb_inv_all(void) "IOTLB invalidate all"
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smmu_iotlb_inv_asid(int asid) "IOTLB invalidate asid=%d"
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smmu_iotlb_inv_asid_vmid(int asid, int vmid) "IOTLB invalidate asid=%d vmid=%d"
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smmu_iotlb_inv_vmid(int vmid) "IOTLB invalidate vmid=%d"
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smmu_iotlb_inv_iova(int asid, uint64_t addr) "IOTLB invalidate asid=%d addr=0x%"PRIx64
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smmu_inv_notifiers_mr(const char *name) "iommu mr=%s"
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@ -213,7 +213,7 @@ void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *entry);
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SMMUIOTLBKey smmu_get_iotlb_key(int asid, int vmid, uint64_t iova,
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uint8_t tg, uint8_t level);
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void smmu_iotlb_inv_all(SMMUState *s);
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void smmu_iotlb_inv_asid(SMMUState *s, int asid);
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void smmu_iotlb_inv_asid_vmid(SMMUState *s, int asid, int vmid);
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void smmu_iotlb_inv_vmid(SMMUState *s, int vmid);
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void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova,
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uint8_t tg, uint64_t num_pages, uint8_t ttl);
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