From ea8618382aba2a7a8a993e61237f2af933fba9ad Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 28 Jun 2024 15:23:39 +0100 Subject: [PATCH] target/arm: Correct comments about M-profile FPSCR The M-profile FPSCR LTPSIZE is bits [18:16]; this is the same field as A-profile FPSCR Len, not Stride. Correct the comment in vfp_get_fpscr(). We also implemented M-profile FPSCR.QC, but forgot to delete a TODO comment from vfp_set_fpscr(); remove it now. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20240628142347.1283015-2-peter.maydell@linaro.org --- target/arm/vfp_helper.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 50d7042fa9..e168600555 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -176,8 +176,8 @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) | (env->vfp.vec_stride << 20); /* - * M-profile LTPSIZE overlaps A-profile Stride; whichever of the - * two is not applicable to this CPU will always be zero. + * M-profile LTPSIZE is the same bits [18:16] as A-profile Len; whichever + * of the two is not applicable to this CPU will always be zero. */ fpscr |= env->v7m.ltpsize << 16; @@ -226,7 +226,6 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) /* * The bit we set within fpscr_q is arbitrary; the register as a * whole being zero/non-zero is what counts. - * TODO: M-profile MVE also has a QC bit. */ env->vfp.qc[0] = val & FPCR_QC; env->vfp.qc[1] = 0;