mirror of https://github.com/xemu-project/xemu.git
ppc440_sdram: Implement enable bit in the DDR2 SDRAM controller
To allow removing the do_init hack we need to improve the DDR2 SDRAM controller model to handle the enable/disable bit that it ignored so far. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <f8900aadb1a4426a6444741e6876c898b3b77f7b.1664021647.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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17221012b1
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@ -485,6 +485,7 @@ void ppc4xx_sdr_init(CPUPPCState *env)
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/* SDRAM controller */
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/* SDRAM controller */
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typedef struct ppc440_sdram_t {
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typedef struct ppc440_sdram_t {
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uint32_t addr;
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uint32_t addr;
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uint32_t mcopt2;
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int nbanks;
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int nbanks;
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Ppc4xxSdramBank bank[4];
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Ppc4xxSdramBank bank[4];
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} ppc440_sdram_t;
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} ppc440_sdram_t;
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@ -600,7 +601,7 @@ static void sdram_map_bcr(ppc440_sdram_t *sdram)
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int i;
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int i;
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for (i = 0; i < sdram->nbanks; i++) {
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for (i = 0; i < sdram->nbanks; i++) {
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if (sdram->bank[i].size != 0) {
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if (sdram->bank[i].size) {
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sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
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sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
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sdram->bank[i].size), 1);
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sdram->bank[i].size), 1);
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} else {
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} else {
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@ -609,6 +610,17 @@ static void sdram_map_bcr(ppc440_sdram_t *sdram)
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}
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}
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}
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}
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static void sdram_unmap_bcr(ppc440_sdram_t *sdram)
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{
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int i;
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for (i = 0; i < sdram->nbanks; i++) {
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if (sdram->bank[i].size) {
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sdram_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
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}
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}
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}
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static uint32_t dcr_read_sdram(void *opaque, int dcrn)
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static uint32_t dcr_read_sdram(void *opaque, int dcrn)
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{
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{
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ppc440_sdram_t *sdram = opaque;
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ppc440_sdram_t *sdram = opaque;
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@ -640,7 +652,7 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
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ret = 0x80000000;
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ret = 0x80000000;
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break;
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break;
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case 0x21: /* SDRAM_MCOPT2 */
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case 0x21: /* SDRAM_MCOPT2 */
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ret = 0x08000000;
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ret = sdram->mcopt2;
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break;
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break;
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case 0x40: /* SDRAM_MB0CF */
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case 0x40: /* SDRAM_MB0CF */
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ret = 0x00008001;
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ret = 0x00008001;
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@ -662,6 +674,8 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
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return ret;
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return ret;
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}
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}
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#define SDRAM_DDR2_MCOPT2_DCEN BIT(27)
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static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
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static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
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{
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{
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ppc440_sdram_t *sdram = opaque;
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ppc440_sdram_t *sdram = opaque;
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@ -684,6 +698,21 @@ static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
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switch (sdram->addr) {
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switch (sdram->addr) {
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case 0x00: /* B0CR */
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case 0x00: /* B0CR */
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break;
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break;
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case 0x21: /* SDRAM_MCOPT2 */
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if (!(sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
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(val & SDRAM_DDR2_MCOPT2_DCEN)) {
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trace_ppc4xx_sdram_enable("enable");
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/* validate all RAM mappings */
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sdram_map_bcr(sdram);
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sdram->mcopt2 |= SDRAM_DDR2_MCOPT2_DCEN;
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} else if ((sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
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!(val & SDRAM_DDR2_MCOPT2_DCEN)) {
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trace_ppc4xx_sdram_enable("disable");
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/* invalidate all RAM mappings */
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sdram_unmap_bcr(sdram);
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sdram->mcopt2 &= ~SDRAM_DDR2_MCOPT2_DCEN;
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}
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break;
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default:
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default:
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break;
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break;
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}
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}
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@ -698,6 +727,7 @@ static void sdram_reset(void *opaque)
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ppc440_sdram_t *sdram = opaque;
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ppc440_sdram_t *sdram = opaque;
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sdram->addr = 0;
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sdram->addr = 0;
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sdram->mcopt2 = SDRAM_DDR2_MCOPT2_DCEN;
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}
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}
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void ppc440_sdram_init(CPUPPCState *env, int nbanks,
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void ppc440_sdram_init(CPUPPCState *env, int nbanks,
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