target: Define TCG_GUEST_DEFAULT_MO in 'cpu-param.h'

accel/tcg/ files requires the following definitions: - TARGET_LONG_BITS - TARGET_PAGE_BITS - TARGET_PHYS_ADDR_SPACE_BITS - TCG_GUEST_DEFAULT_MO The first 3 are defined in "cpu-param.h". The last one in "cpu.h", with a bunch of definitions irrelevant for TCG. By moving the TCG_GUEST_DEFAULT_MO definition to "cpu-param.h", we can simplify various accel/tcg includes. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20231211212003.21686-4-philmd@linaro.org>
2023-12-05 14:31:59 +01:00 · 2023-12-05 14:31:59 +01:00 · e92dd33224
parent 83fb360d6a
commit e92dd33224
28 changed files with 66 additions and 62 deletions
--- a/target/alpha/cpu-param.h
+++ b/target/alpha/cpu-param.h
@ -27,4 +27,7 @@
 # define TARGET_VIRT_ADDR_SPACE_BITS  (30 + TARGET_PAGE_BITS)
 #endif

+/* Alpha processors have a weak memory model */
+#define TCG_GUEST_DEFAULT_MO      (0)
+
 #endif
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@ -24,9 +24,6 @@
 #include "exec/cpu-defs.h"
 #include "qemu/cpu-float.h"

-/* Alpha processors have a weak memory model */
-#define TCG_GUEST_DEFAULT_MO      (0)
-
 #define ICACHE_LINE_SIZE 32
 #define DCACHE_LINE_SIZE 32

--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@ -27,14 +27,16 @@
 # else
 #  define TARGET_PAGE_BITS 12
 # endif
-#else
+#else /* !CONFIG_USER_ONLY */
 /*
 * ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6
 * have to support 1K tiny pages.
 */
 # define TARGET_PAGE_BITS_VARY
 # define TARGET_PAGE_BITS_MIN  10
-
-#endif
+#endif /* !CONFIG_USER_ONLY */
+
+/* ARM processors have a weak memory model */
+#define TCG_GUEST_DEFAULT_MO      (0)

 #endif
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@ -30,9 +30,6 @@
 #include "target/arm/multiprocessing.h"
 #include "target/arm/gtimer.h"

-/* ARM processors have a weak memory model */
-#define TCG_GUEST_DEFAULT_MO      (0)
-
 #ifdef TARGET_AARCH64
 #define KVM_HAVE_MCE_INJECTION 1
 #endif
--- a/target/avr/cpu-param.h
+++ b/target/avr/cpu-param.h
@ -32,4 +32,6 @@
 #define TARGET_PHYS_ADDR_SPACE_BITS 24
 #define TARGET_VIRT_ADDR_SPACE_BITS 24

+#define TCG_GUEST_DEFAULT_MO 0
+
 #endif
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@ -30,8 +30,6 @@

 #define CPU_RESOLVING_TYPE TYPE_AVR_CPU

-#define TCG_GUEST_DEFAULT_MO 0
-
 /*
 * AVR has two memory spaces, data & code.
 * e.g. both have 0 address
--- a/target/hppa/cpu-param.h
+++ b/target/hppa/cpu-param.h
@ -21,4 +21,12 @@

 #define TARGET_PAGE_BITS 12

+/* PA-RISC 1.x processors have a strong memory model.  */
+/*
+ * ??? While we do not yet implement PA-RISC 2.0, those processors have
+ * a weak memory model, but with TLB bits that force ordering on a per-page
+ * basis.  It's probably easier to fall back to a strong memory model.
+ */
+#define TCG_GUEST_DEFAULT_MO        TCG_MO_ALL
+
 #endif
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@ -25,12 +25,6 @@
 #include "qemu/cpu-float.h"
 #include "qemu/interval-tree.h"

-/* PA-RISC 1.x processors have a strong memory model.  */
-/* ??? While we do not yet implement PA-RISC 2.0, those processors have
-   a weak memory model, but with TLB bits that force ordering on a per-page
-   basis.  It's probably easier to fall back to a strong memory model.  */
-#define TCG_GUEST_DEFAULT_MO        TCG_MO_ALL
-
 #define MMU_ABS_W_IDX     6
 #define MMU_ABS_IDX       7
 #define MMU_KERNEL_IDX    8
--- a/target/i386/cpu-param.h
+++ b/target/i386/cpu-param.h
@ -24,4 +24,7 @@
 #endif
 #define TARGET_PAGE_BITS 12

+/* The x86 has a strong memory model with some store-after-load re-ordering */
+#define TCG_GUEST_DEFAULT_MO      (TCG_MO_ALL & ~TCG_MO_ST_LD)
+
 #endif
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@ -30,9 +30,6 @@

 #define XEN_NR_VIRQS 24

-/* The x86 has a strong memory model with some store-after-load re-ordering */
-#define TCG_GUEST_DEFAULT_MO      (TCG_MO_ALL & ~TCG_MO_ST_LD)
-
 #define KVM_HAVE_MCE_INJECTION 1

 /* support for self modifying code even if the modified instruction is
--- a/target/loongarch/cpu-param.h
+++ b/target/loongarch/cpu-param.h
@ -14,4 +14,6 @@

 #define TARGET_PAGE_BITS 12

+#define TCG_GUEST_DEFAULT_MO (0)
+
 #endif
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@ -39,8 +39,6 @@

 #define IOCSR_MEM_SIZE          0x428

-#define TCG_GUEST_DEFAULT_MO (0)
-
 #define FCSR0_M1    0x1f         /* FCSR1 mask, Enables */
 #define FCSR0_M2    0x1f1f0000   /* FCSR2 mask, Cause and Flags */
 #define FCSR0_M3    0x300        /* FCSR3 mask, Round Mode */
--- a/target/microblaze/cpu-param.h
+++ b/target/microblaze/cpu-param.h
@ -29,4 +29,7 @@
 /* FIXME: MB uses variable pages down to 1K but linux only uses 4k.  */
 #define TARGET_PAGE_BITS 12

+/* MicroBlaze is always in-order. */
+#define TCG_GUEST_DEFAULT_MO  TCG_MO_ALL
+
 #endif
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@ -24,9 +24,6 @@
 #include "exec/cpu-defs.h"
 #include "qemu/cpu-float.h"

-/* MicroBlaze is always in-order. */
-#define TCG_GUEST_DEFAULT_MO  TCG_MO_ALL
-
 typedef struct CPUArchState CPUMBState;
 #if !defined(CONFIG_USER_ONLY)
 #include "mmu.h"
--- a/target/mips/cpu-param.h
+++ b/target/mips/cpu-param.h
@ -30,4 +30,6 @@
 #define TARGET_PAGE_BITS_MIN 12
 #endif

+#define TCG_GUEST_DEFAULT_MO (0)
+
 #endif
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@ -10,8 +10,6 @@
 #include "hw/clock.h"
 #include "mips-defs.h"

-#define TCG_GUEST_DEFAULT_MO (0)
-
 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;

 /* MSA Context */
--- a/target/openrisc/cpu-param.h
+++ b/target/openrisc/cpu-param.h
@ -13,4 +13,6 @@
 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 #define TARGET_VIRT_ADDR_SPACE_BITS 32

+#define TCG_GUEST_DEFAULT_MO (0)
+
 #endif
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@ -24,8 +24,6 @@
 #include "exec/cpu-defs.h"
 #include "fpu/softfloat-types.h"

-#define TCG_GUEST_DEFAULT_MO (0)
-
 /**
 * OpenRISCCPUClass:
 * @parent_realize: The parent class' realize handler.
--- a/target/ppc/cpu-param.h
+++ b/target/ppc/cpu-param.h
@ -40,4 +40,6 @@
 # define TARGET_PAGE_BITS 12
 #endif

+#define TCG_GUEST_DEFAULT_MO 0
+
 #endif
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@ -29,8 +29,6 @@

 #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU

-#define TCG_GUEST_DEFAULT_MO 0
-
 #define TARGET_PAGE_BITS_64K 16
 #define TARGET_PAGE_BITS_16M 24

--- a/target/riscv/cpu-param.h
+++ b/target/riscv/cpu-param.h
@ -28,4 +28,6 @@
 *  - M mode HLV/HLVX/HSV 0b111
 */

+#define TCG_GUEST_DEFAULT_MO 0
+
 #endif
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@ -43,8 +43,6 @@ typedef struct CPUArchState CPURISCVState;
 # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
 #endif

-#define TCG_GUEST_DEFAULT_MO 0
-
 /*
 * RISC-V-specific extra insn start words:
 * 1: Original instruction opcode
--- a/target/s390x/cpu-param.h
+++ b/target/s390x/cpu-param.h
@ -13,4 +13,10 @@
 #define TARGET_PHYS_ADDR_SPACE_BITS 64
 #define TARGET_VIRT_ADDR_SPACE_BITS 64

+/*
+ * The z/Architecture has a strong memory model with some
+ * store-after-load re-ordering.
+ */
+#define TCG_GUEST_DEFAULT_MO      (TCG_MO_ALL & ~TCG_MO_ST_LD)
+
 #endif
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@ -33,9 +33,6 @@

 #define ELF_MACHINE_UNAME "S390X"

-/* The z/Architecture has a strong memory model with some store-after-load re-ordering */
-#define TCG_GUEST_DEFAULT_MO      (TCG_MO_ALL & ~TCG_MO_ST_LD)
-
 #define TARGET_HAS_PRECISE_SMC

 #define TARGET_INSN_START_EXTRA_WORDS 2
--- a/target/sparc/cpu-param.h
+++ b/target/sparc/cpu-param.h
@ -23,4 +23,27 @@
 # define TARGET_VIRT_ADDR_SPACE_BITS 32
 #endif

+/*
+ * From Oracle SPARC Architecture 2015:
+ *
+ *   Compatibility notes: The PSO memory model described in SPARC V8 and
+ *   SPARC V9 compatibility architecture specifications was never implemented
+ *   in a SPARC V9 implementation and is not included in the Oracle SPARC
+ *   Architecture specification.
+ *
+ *   The RMO memory model described in the SPARC V9 specification was
+ *   implemented in some non-Sun SPARC V9 implementations, but is not
+ *   directly supported in Oracle SPARC Architecture 2015 implementations.
+ *
+ * Therefore always use TSO in QEMU.
+ *
+ * D.5 Specification of Partial Store Order (PSO)
+ *   ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore.
+ *
+ * D.6 Specification of Total Store Order (TSO)
+ *   ... PSO with the additional requirement that all [stores] are followed
+ *   by an implied MEMBAR #StoreStore.
+ */
+#define TCG_GUEST_DEFAULT_MO  (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST)
+
 #endif
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@ -6,29 +6,6 @@
 #include "exec/cpu-defs.h"
 #include "qemu/cpu-float.h"

-/*
- * From Oracle SPARC Architecture 2015:
- *
- *   Compatibility notes: The PSO memory model described in SPARC V8 and
- *   SPARC V9 compatibility architecture specifications was never implemented
- *   in a SPARC V9 implementation and is not included in the Oracle SPARC
- *   Architecture specification.
- *
- *   The RMO memory model described in the SPARC V9 specification was
- *   implemented in some non-Sun SPARC V9 implementations, but is not
- *   directly supported in Oracle SPARC Architecture 2015 implementations.
- *
- * Therefore always use TSO in QEMU.
- *
- * D.5 Specification of Partial Store Order (PSO)
- *   ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore.
- *
- * D.6 Specification of Total Store Order (TSO)
- *   ... PSO with the additional requirement that all [stores] are followed
- *   by an implied MEMBAR #StoreStore.
- */
-#define TCG_GUEST_DEFAULT_MO  (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST)
-
 #if !defined(TARGET_SPARC64)
 #define TARGET_DPREGS 16
 #define TARGET_FCCREGS 1
--- a/target/xtensa/cpu-param.h
+++ b/target/xtensa/cpu-param.h
@ -17,4 +17,7 @@
 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 #endif

+/* Xtensa processors have a weak memory model */
+#define TCG_GUEST_DEFAULT_MO      (0)
+
 #endif
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@ -34,9 +34,6 @@
 #include "hw/clock.h"
 #include "xtensa-isa.h"

-/* Xtensa processors have a weak memory model */
-#define TCG_GUEST_DEFAULT_MO      (0)
-
 enum {
    /* Additional instructions */
    XTENSA_OPTION_CODE_DENSITY,