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* IEC units series (Philippe) 

* Hyper-V PV TLB flush (Vitaly)
 * git archive detection (Daniel)
 * host serial passthrough fix (David)
 * NPT support for SVM emulation (Jan)
 * x86 "info mem" and "info tlb" fix (Doug)
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2.0.22 (GNU/Linux)
 
 iQEcBAABAgAGBQJbOkI9AAoJEL/70l94x66DaA0IAIzJD+3hUdwDCqitlW65x/yX
 D+KAoX4Ytpz7+QOtcXC7BBUW3JwvHTS5sfuvaAqKWnqEXSDrQs4/gG2iEB1UJ3Ko
 hC2LHGKygdcD9k3vuQ2q2USOu08jEUYRvvjgHmD6lsyaAQ+cb2heAYz/SxQqbkkt
 qun6TFaWuTGBQF1qy0xjJitdPokGwFZgprlZyVmMId/yLlsbsFlwmGIJh/l1+zqw
 I4DBzRzuhAg/nLH9qVZ3LWOjH1H0MLPGBUG59w4GbIDpwRh1VZu+GTyAmAYaquHl
 dSHYweXywNTvhi0WLroP8SD0Nqf/ZObuSRtop60gqJuP3YAbPrBMeRTlsqoZIRE=
 =Xzc8
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging

* IEC units series (Philippe)
* Hyper-V PV TLB flush (Vitaly)
* git archive detection (Daniel)
* host serial passthrough fix (David)
* NPT support for SVM emulation (Jan)
* x86 "info mem" and "info tlb" fix (Doug)

# gpg: Signature made Mon 02 Jul 2018 16:18:21 BST
# gpg:                using RSA key BFFBD25F78C7AE83
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>"
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>"
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* remotes/bonzini/tags/for-upstream: (50 commits)
  tcg: simplify !CONFIG_TCG handling of tb_invalidate_*
  i386/monitor.c: make addresses canonical for "info mem" and "info tlb"
  target-i386: Add NPT support
  serial: Open non-block
  bsd-user: Use the IEC binary prefix definitions
  linux-user: Use the IEC binary prefix definitions
  tests/crypto: Use the IEC binary prefix definitions
  vl: Use the IEC binary prefix definitions
  monitor: Use the IEC binary prefix definitions
  cutils: Do not include "qemu/units.h" directly
  hw/rdma: Use the IEC binary prefix definitions
  hw/virtio: Use the IEC binary prefix definitions
  hw/vfio: Use the IEC binary prefix definitions
  hw/sd: Use the IEC binary prefix definitions
  hw/usb: Use the IEC binary prefix definitions
  hw/net: Use the IEC binary prefix definitions
  hw/i386: Use the IEC binary prefix definitions
  hw/ppc: Use the IEC binary prefix definitions
  hw/mips: Use the IEC binary prefix definitions
  hw/mips/r4k: Constify params_size
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2018-07-02 19:07:19 +01:00
parent ab08440a4e c40d479207
commit e8c858944e
129 changed files with 840 additions and 440 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
accel/stubs/tcg-stub.c
View File

@ -16,7 +16,6 @@
#include "tcg/tcg.h" #include "tcg/tcg.h"
#include "exec/cpu-common.h" #include "exec/cpu-common.h"
#include "exec/exec-all.h" #include "exec/exec-all.h"
#include "translate-all.h"
void tb_flush(CPUState *cpu) void tb_flush(CPUState *cpu)
{ {
@ -25,8 +24,3 @@ void tb_flush(CPUState *cpu)
void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) void tlb_set_dirty(CPUState *cpu, target_ulong vaddr)
{ {
} }
void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
int is_cpu_write_access)
{
}

7
block/vdi.c
View File

@ -50,6 +50,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qapi/qobject-input-visitor.h" #include "qapi/qobject-input-visitor.h"
#include "qapi/qapi-visit-block-core.h" #include "qapi/qapi-visit-block-core.h"
@ -83,9 +84,6 @@
/* Command line option for static images. */ /* Command line option for static images. */
#define BLOCK_OPT_STATIC "static" #define BLOCK_OPT_STATIC "static"
#define KiB 1024
#define MiB (KiB * KiB)
#define SECTOR_SIZE 512 #define SECTOR_SIZE 512
#define DEFAULT_CLUSTER_SIZE (1 * MiB) #define DEFAULT_CLUSTER_SIZE (1 * MiB)
@ -434,7 +432,8 @@ static int vdi_open(BlockDriverState *bs, QDict *options, int flags,
goto fail; goto fail;
} else if (header.block_size != DEFAULT_CLUSTER_SIZE) { } else if (header.block_size != DEFAULT_CLUSTER_SIZE) {
error_setg(errp, "unsupported VDI image (block size %" PRIu32 error_setg(errp, "unsupported VDI image (block size %" PRIu32
" is not %u)", header.block_size, DEFAULT_CLUSTER_SIZE); " is not %" PRIu64 ")",
header.block_size, DEFAULT_CLUSTER_SIZE);
ret = -ENOTSUP; ret = -ENOTSUP;
goto fail; goto fail;
} else if (header.disk_size > } else if (header.disk_size >

5
bsd-user/main.c
View File

@ -17,6 +17,7 @@
* along with this program; if not, see <http://www.gnu.org/licenses/>. * along with this program; if not, see <http://www.gnu.org/licenses/>.
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu-version.h" #include "qemu-version.h"
#include <machine/trap.h> #include <machine/trap.h>
@ -795,9 +796,9 @@ int main(int argc, char **argv)
if (x86_stack_size <= 0) if (x86_stack_size <= 0)
usage(); usage();
if (*r == 'M') if (*r == 'M')
x86_stack_size *= 1024 * 1024; x86_stack_size *= MiB;
else if (*r == 'k' || *r == 'K') else if (*r == 'k' || *r == 'K')
x86_stack_size *= 1024; x86_stack_size *= KiB;
} else if (!strcmp(r, "L")) { } else if (!strcmp(r, "L")) {
interp_prefix = argv[optind++]; interp_prefix = argv[optind++];
} else if (!strcmp(r, "p")) { } else if (!strcmp(r, "p")) {

3
chardev/char-serial.c
View File

@ -265,7 +265,8 @@ static void qmp_chardev_open_serial(Chardev *chr,
ChardevHostdev *serial = backend->u.serial.data; ChardevHostdev *serial = backend->u.serial.data;
int fd; int fd;
fd = qmp_chardev_open_file_source(serial->device, O_RDWR, errp); fd = qmp_chardev_open_file_source(serial->device, O_RDWR | O_NONBLOCK,
errp);
if (fd < 0) { if (fd < 0) {
return; return;
} }

18
configure vendored
View File

@ -300,6 +300,24 @@ then
else else
git_update=no git_update=no
git_submodules="" git_submodules=""
if ! test -f "$source_path/ui/keycodemapdb/README"
then
echo
echo "ERROR: missing file $source_path/ui/keycodemapdb/README"
echo
echo "This is not a GIT checkout but module content appears to"
echo "be missing. Do not use 'git archive' or GitHub download links"
echo "to acquire QEMU source archives. Non-GIT builds are only"
echo "supported with source archives linked from:"
echo
echo " https://www.qemu.org/download/"
echo
echo "Developers working with GIT can use scripts/archive-source.sh"
echo "if they need to create valid source archives."
echo
exit 1
fi
fi fi
git="git" git="git"

6
exec.c
View File

@ -1027,7 +1027,7 @@ const char *parse_cpu_model(const char *cpu_model)
return cpu_type; return cpu_type;
} }
#if defined(CONFIG_USER_ONLY) || !defined(CONFIG_TCG) #if defined(CONFIG_USER_ONLY)
void tb_invalidate_phys_addr(target_ulong addr) void tb_invalidate_phys_addr(target_ulong addr)
{ {
mmap_lock(); mmap_lock();
@ -1046,6 +1046,10 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
MemoryRegion *mr; MemoryRegion *mr;
hwaddr l = 1; hwaddr l = 1;
if (!tcg_enabled()) {
return;
}
rcu_read_lock(); rcu_read_lock();
mr = address_space_translate(as, addr, &addr, &l, false, attrs); mr = address_space_translate(as, addr, &addr, &l, false, attrs);
if (!(memory_region_is_ram(mr) if (!(memory_region_is_ram(mr)

17
hw/alpha/typhoon.c
View File

@ -7,6 +7,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "cpu.h" #include "cpu.h"
#include "hw/hw.h" #include "hw/hw.h"
@ -813,8 +814,6 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
qemu_irq *p_rtc_irq, qemu_irq *p_rtc_irq,
AlphaCPU *cpus[4], pci_map_irq_fn sys_map_irq) AlphaCPU *cpus[4], pci_map_irq_fn sys_map_irq)
{ {
const uint64_t MB = 1024 * 1024;
const uint64_t GB = 1024 * MB;
MemoryRegion *addr_space = get_system_memory(); MemoryRegion *addr_space = get_system_memory();
DeviceState *dev; DeviceState *dev;
TyphoonState *s; TyphoonState *s;
@ -855,30 +854,30 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
/* Pchip0 CSRs, 0x801.8000.0000, 256MB. */ /* Pchip0 CSRs, 0x801.8000.0000, 256MB. */
memory_region_init_io(&s->pchip.region, OBJECT(s), &pchip_ops, s, "pchip0", memory_region_init_io(&s->pchip.region, OBJECT(s), &pchip_ops, s, "pchip0",
256*MB); 256 * MiB);
memory_region_add_subregion(addr_space, 0x80180000000ULL, memory_region_add_subregion(addr_space, 0x80180000000ULL,
&s->pchip.region); &s->pchip.region);
/* Cchip CSRs, 0x801.A000.0000, 256MB. */ /* Cchip CSRs, 0x801.A000.0000, 256MB. */
memory_region_init_io(&s->cchip.region, OBJECT(s), &cchip_ops, s, "cchip0", memory_region_init_io(&s->cchip.region, OBJECT(s), &cchip_ops, s, "cchip0",
256*MB); 256 * MiB);
memory_region_add_subregion(addr_space, 0x801a0000000ULL, memory_region_add_subregion(addr_space, 0x801a0000000ULL,
&s->cchip.region); &s->cchip.region);
/* Dchip CSRs, 0x801.B000.0000, 256MB. */ /* Dchip CSRs, 0x801.B000.0000, 256MB. */
memory_region_init_io(&s->dchip_region, OBJECT(s), &dchip_ops, s, "dchip0", memory_region_init_io(&s->dchip_region, OBJECT(s), &dchip_ops, s, "dchip0",
256*MB); 256 * MiB);
memory_region_add_subregion(addr_space, 0x801b0000000ULL, memory_region_add_subregion(addr_space, 0x801b0000000ULL,
&s->dchip_region); &s->dchip_region);
/* Pchip0 PCI memory, 0x800.0000.0000, 4GB. */ /* Pchip0 PCI memory, 0x800.0000.0000, 4GB. */
memory_region_init(&s->pchip.reg_mem, OBJECT(s), "pci0-mem", 4*GB); memory_region_init(&s->pchip.reg_mem, OBJECT(s), "pci0-mem", 4 * GiB);
memory_region_add_subregion(addr_space, 0x80000000000ULL, memory_region_add_subregion(addr_space, 0x80000000000ULL,
&s->pchip.reg_mem); &s->pchip.reg_mem);
/* Pchip0 PCI I/O, 0x801.FC00.0000, 32MB. */ /* Pchip0 PCI I/O, 0x801.FC00.0000, 32MB. */
memory_region_init_io(&s->pchip.reg_io, OBJECT(s), &alpha_pci_ignore_ops, memory_region_init_io(&s->pchip.reg_io, OBJECT(s), &alpha_pci_ignore_ops,
NULL, "pci0-io", 32*MB); NULL, "pci0-io", 32 * MiB);
memory_region_add_subregion(addr_space, 0x801fc000000ULL, memory_region_add_subregion(addr_space, 0x801fc000000ULL,
&s->pchip.reg_io); &s->pchip.reg_io);
@ -899,13 +898,13 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
/* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB. */ /* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB. */
memory_region_init_io(&s->pchip.reg_iack, OBJECT(s), &alpha_pci_iack_ops, memory_region_init_io(&s->pchip.reg_iack, OBJECT(s), &alpha_pci_iack_ops,
b, "pci0-iack", 64*MB); b, "pci0-iack", 64 * MiB);
memory_region_add_subregion(addr_space, 0x801f8000000ULL, memory_region_add_subregion(addr_space, 0x801f8000000ULL,
&s->pchip.reg_iack); &s->pchip.reg_iack);
/* Pchip0 PCI configuration, 0x801.FE00.0000, 16MB. */ /* Pchip0 PCI configuration, 0x801.FE00.0000, 16MB. */
memory_region_init_io(&s->pchip.reg_conf, OBJECT(s), &alpha_pci_conf1_ops, memory_region_init_io(&s->pchip.reg_conf, OBJECT(s), &alpha_pci_conf1_ops,
b, "pci0-conf", 16*MB); b, "pci0-conf", 16 * MiB);
memory_region_add_subregion(addr_space, 0x801fe000000ULL, memory_region_add_subregion(addr_space, 0x801fe000000ULL,
&s->pchip.reg_conf); &s->pchip.reg_conf);

6
hw/arm/msf2-soc.c
View File

@ -23,13 +23,13 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "hw/arm/arm.h" #include "hw/arm/arm.h"
#include "exec/address-spaces.h" #include "exec/address-spaces.h"
#include "hw/char/serial.h" #include "hw/char/serial.h"
#include "hw/boards.h" #include "hw/boards.h"
#include "qemu/cutils.h"
#include "hw/arm/msf2-soc.h" #include "hw/arm/msf2-soc.h"
#include "hw/misc/unimp.h" #include "hw/misc/unimp.h"
@ -40,14 +40,14 @@
#define SRAM_BASE_ADDRESS 0x20000000 #define SRAM_BASE_ADDRESS 0x20000000
#define MSF2_ENVM_MAX_SIZE (512 * K_BYTE) #define MSF2_ENVM_MAX_SIZE (512 * KiB)
/* /*
* eSRAM max size is 80k without SECDED(Single error correction and * eSRAM max size is 80k without SECDED(Single error correction and
* dual error detection) feature and 64k with SECDED. * dual error detection) feature and 64k with SECDED.
* We do not support SECDED now. * We do not support SECDED now.
*/ */
#define MSF2_ESRAM_MAX_SIZE (80 * K_BYTE) #define MSF2_ESRAM_MAX_SIZE (80 * KiB)
static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 }; static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 }; static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };

8
hw/arm/msf2-som.c
View File

@ -23,20 +23,20 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
#include "hw/boards.h" #include "hw/boards.h"
#include "hw/arm/arm.h" #include "hw/arm/arm.h"
#include "exec/address-spaces.h" #include "exec/address-spaces.h"
#include "qemu/cutils.h"
#include "hw/arm/msf2-soc.h" #include "hw/arm/msf2-soc.h"
#include "cpu.h" #include "cpu.h"
#define DDR_BASE_ADDRESS 0xA0000000 #define DDR_BASE_ADDRESS 0xA0000000
#define DDR_SIZE (64 * M_BYTE) #define DDR_SIZE (64 * MiB)
#define M2S010_ENVM_SIZE (256 * K_BYTE) #define M2S010_ENVM_SIZE (256 * KiB)
#define M2S010_ESRAM_SIZE (64 * K_BYTE) #define M2S010_ESRAM_SIZE (64 * KiB)
static void emcraft_sf2_s2s010_init(MachineState *machine) static void emcraft_sf2_s2s010_init(MachineState *machine)
{ {

5
hw/block/m25p80.c
View File

@ -22,6 +22,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "sysemu/block-backend.h" #include "sysemu/block-backend.h"
#include "hw/ssi/ssi.h" #include "hw/ssi/ssi.h"
@ -541,12 +542,12 @@ static void flash_erase(Flash *s, int offset, FlashCMD cmd)
switch (cmd) { switch (cmd) {
case ERASE_4K: case ERASE_4K:
case ERASE4_4K: case ERASE4_4K:
len = 4 << 10; len = 4 * KiB;
capa_to_assert = ER_4K; capa_to_assert = ER_4K;
break; break;
case ERASE_32K: case ERASE_32K:
case ERASE4_32K: case ERASE4_32K:
len = 32 << 10; len = 32 * KiB;
capa_to_assert = ER_32K; capa_to_assert = ER_32K;
break; break;
case ERASE_SECTOR: case ERASE_SECTOR:

3
hw/block/nvme.c
View File

@ -26,6 +26,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/block/block.h" #include "hw/block/block.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "hw/pci/msix.h" #include "hw/pci/msix.h"
@ -649,7 +650,7 @@ static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeIdentify *c)
static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeIdentify *c) static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeIdentify *c)
{ {
static const int data_len = 4096; static const int data_len = 4 * KiB;
uint32_t min_nsid = le32_to_cpu(c->nsid); uint32_t min_nsid = le32_to_cpu(c->nsid);
uint64_t prp1 = le64_to_cpu(c->prp1); uint64_t prp1 = le64_to_cpu(c->prp1);
uint64_t prp2 = le64_to_cpu(c->prp2); uint64_t prp2 = le64_to_cpu(c->prp2);

3
hw/block/tc58128.c
View File

@ -1,4 +1,5 @@
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "hw/sh4/sh.h" #include "hw/sh4/sh.h"
#include "hw/loader.h" #include "hw/loader.h"
@ -26,7 +27,7 @@ typedef struct {
static tc58128_dev tc58128_devs[2]; static tc58128_dev tc58128_devs[2];
#define FLASH_SIZE (16*1024*1024) #define FLASH_SIZE (16 * MiB)
static void init_dev(tc58128_dev * dev, const char *filename) static void init_dev(tc58128_dev * dev, const char *filename)
{ {

3
hw/block/xen_disk.c
View File

@ -20,6 +20,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include <sys/ioctl.h> #include <sys/ioctl.h>
#include <sys/uio.h> #include <sys/uio.h>
@ -814,7 +815,7 @@ static int blk_connect(struct XenDevice *xendev)
xen_pv_printf(xendev, 1, "type \"%s\", fileproto \"%s\", filename \"%s\"," xen_pv_printf(xendev, 1, "type \"%s\", fileproto \"%s\", filename \"%s\","
" size %" PRId64 " (%" PRId64 " MB)\n", " size %" PRId64 " (%" PRId64 " MB)\n",
blkdev->type, blkdev->fileproto, blkdev->filename, blkdev->type, blkdev->fileproto, blkdev->filename,
blkdev->file_size, blkdev->file_size >> 20); blkdev->file_size, blkdev->file_size / MiB);
/* Fill in number of sector size and number of sectors */ /* Fill in number of sector size and number of sectors */
xenstore_write_be_int(xendev, "sector-size", blkdev->file_blk); xenstore_write_be_int(xendev, "sector-size", blkdev->file_blk);

3
hw/core/loader-fit.c
View File

@ -18,6 +18,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "exec/memory.h" #include "exec/memory.h"
#include "hw/loader.h" #include "hw/loader.h"
#include "hw/loader-fit.h" #include "hw/loader-fit.h"
@ -194,7 +195,7 @@ static int fit_load_fdt(const struct fit_loader *ldr, const void *itb,
err = fit_image_addr(itb, img_off, "load", &load_addr); err = fit_image_addr(itb, img_off, "load", &load_addr);
if (err == -ENOENT) { if (err == -ENOENT) {
load_addr = ROUND_UP(kernel_end, 64 * K_BYTE) + (10 * M_BYTE); load_addr = ROUND_UP(kernel_end, 64 * KiB) + (10 * MiB);
} else if (err) { } else if (err) {
ret = err; ret = err;
goto out; goto out;

4
hw/core/machine.c
View File

@ -11,6 +11,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/boards.h" #include "hw/boards.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qapi/qapi-visit-common.h" #include "qapi/qapi-visit-common.h"
@ -19,7 +20,6 @@
#include "sysemu/sysemu.h" #include "sysemu/sysemu.h"
#include "sysemu/numa.h" #include "sysemu/numa.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
#include "qemu/cutils.h"
#include "sysemu/qtest.h" #include "sysemu/qtest.h"
static char *machine_get_accel(Object *obj, Error **errp) static char *machine_get_accel(Object *obj, Error **errp)
@ -522,7 +522,7 @@ static void machine_class_init(ObjectClass *oc, void *data)
MachineClass *mc = MACHINE_CLASS(oc); MachineClass *mc = MACHINE_CLASS(oc);
/* Default 128 MB as guest ram size */ /* Default 128 MB as guest ram size */
mc->default_ram_size = 128 * M_BYTE; mc->default_ram_size = 128 * MiB;
mc->rom_file_has_mr = true; mc->rom_file_has_mr = true;
/* numa node memory size aligned on 8MB by default. /* numa node memory size aligned on 8MB by default.

3
hw/cris/axis_dev88.c
View File

@ -23,6 +23,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "cpu.h" #include "cpu.h"
@ -242,7 +243,7 @@ static const MemoryRegionOps gpio_ops = {
}, },
}; };
#define INTMEM_SIZE (128 * 1024) #define INTMEM_SIZE (128 * KiB)
static struct cris_load_info li; static struct cris_load_info li;

9
hw/display/bochs-display.c
View File

@ -5,6 +5,7 @@
* See the COPYING file in the top-level directory. * See the COPYING file in the top-level directory.
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "hw/pci/pci.h" #include "hw/pci/pci.h"
#include "hw/display/bochs-vbe.h" #include "hw/display/bochs-vbe.h"
@ -70,7 +71,7 @@ static uint64_t bochs_display_vbe_read(void *ptr, hwaddr addr,
case VBE_DISPI_INDEX_ID: case VBE_DISPI_INDEX_ID:
return VBE_DISPI_ID5; return VBE_DISPI_ID5;
case VBE_DISPI_INDEX_VIDEO_MEMORY_64K: case VBE_DISPI_INDEX_VIDEO_MEMORY_64K:
return s->vgamem / (64 * 1024); return s->vgamem / (64 * KiB);
} }
if (index >= ARRAY_SIZE(s->vbe_regs)) { if (index >= ARRAY_SIZE(s->vbe_regs)) {
@ -258,10 +259,10 @@ static void bochs_display_realize(PCIDevice *dev, Error **errp)
s->con = graphic_console_init(DEVICE(dev), 0, &bochs_display_gfx_ops, s); s->con = graphic_console_init(DEVICE(dev), 0, &bochs_display_gfx_ops, s);
if (s->vgamem < (4 * 1024 * 1024)) { if (s->vgamem < 4 * MiB) {
error_setg(errp, "bochs-display: video memory too small"); error_setg(errp, "bochs-display: video memory too small");
} }
if (s->vgamem > (256 * 1024 * 1024)) { if (s->vgamem > 256 * MiB) {
error_setg(errp, "bochs-display: video memory too big"); error_setg(errp, "bochs-display: video memory too big");
} }
s->vgamem = pow2ceil(s->vgamem); s->vgamem = pow2ceil(s->vgamem);
@ -323,7 +324,7 @@ static void bochs_display_exit(PCIDevice *dev)
} }
static Property bochs_display_properties[] = { static Property bochs_display_properties[] = {
DEFINE_PROP_SIZE("vgamem", BochsDisplayState, vgamem, 16 * 1024 * 1024), DEFINE_PROP_SIZE("vgamem", BochsDisplayState, vgamem, 16 * MiB),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),
}; };

10
hw/display/cirrus_vga.c
View File

@ -27,6 +27,7 @@
* available at http://home.worldonline.dk/~finth/ * available at http://home.worldonline.dk/~finth/
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "trace.h" #include "trace.h"
#include "hw/hw.h" #include "hw/hw.h"
@ -2218,7 +2219,7 @@ static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
uint32_t content; uint32_t content;
int y, y_min, y_max; int y, y_min, y_max;
src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024; src = s->vga.vram_ptr + s->real_vram_size - 16 * KiB;
if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
src += (s->vga.sr[0x13] & 0x3c) * 256; src += (s->vga.sr[0x13] & 0x3c) * 256;
y_min = 64; y_min = 64;
@ -2347,7 +2348,7 @@ static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
return; return;
} }
src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024; src = s->vga.vram_ptr + s->real_vram_size - 16 * KiB;
if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
src += (s->vga.sr[0x13] & 0x3c) * 256; src += (s->vga.sr[0x13] & 0x3c) * 256;
src += (scr_y - s->vga.hw_cursor_y) * 16; src += (scr_y - s->vga.hw_cursor_y) * 16;
@ -2995,8 +2996,7 @@ static void cirrus_init_common(CirrusVGAState *s, Object *owner,
/* I/O handler for LFB */ /* I/O handler for LFB */
memory_region_init_io(&s->cirrus_linear_io, owner, &cirrus_linear_io_ops, s, memory_region_init_io(&s->cirrus_linear_io, owner, &cirrus_linear_io_ops, s,
"cirrus-linear-io", s->vga.vram_size_mb "cirrus-linear-io", s->vga.vram_size_mb * MiB);
* 1024 * 1024);
memory_region_set_flush_coalesced(&s->cirrus_linear_io); memory_region_set_flush_coalesced(&s->cirrus_linear_io);
/* I/O handler for LFB */ /* I/O handler for LFB */
@ -3013,7 +3013,7 @@ static void cirrus_init_common(CirrusVGAState *s, Object *owner,
memory_region_set_flush_coalesced(&s->cirrus_mmio_io); memory_region_set_flush_coalesced(&s->cirrus_mmio_io);
s->real_vram_size = s->real_vram_size =
(s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024; (s->device_id == CIRRUS_ID_CLGD5446) ? 4 * MiB : 2 * MiB;
/* XXX: s->vga.vram_size must be a power of two */ /* XXX: s->vga.vram_size must be a power of two */
s->cirrus_addr_mask = s->real_vram_size - 1; s->cirrus_addr_mask = s->real_vram_size - 1;

4
hw/display/g364fb.c
View File

@ -18,6 +18,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
#include "ui/console.h" #include "ui/console.h"
@ -510,8 +511,7 @@ static void g364fb_sysbus_reset(DeviceState *d)
} }
static Property g364fb_sysbus_properties[] = { static Property g364fb_sysbus_properties[] = {
DEFINE_PROP_UINT32("vram_size", G364SysBusState, g364.vram_size, DEFINE_PROP_UINT32("vram_size", G364SysBusState, g364.vram_size, 8 * MiB),
8 * 1024 * 1024),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),
}; };

30
hw/display/qxl.c
View File

@ -19,6 +19,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include <zlib.h> #include <zlib.h>
#include "qapi/error.h" #include "qapi/error.h"
@ -2012,11 +2013,11 @@ static void qxl_init_ramsize(PCIQXLDevice *qxl)
if (qxl->vgamem_size_mb > 256) { if (qxl->vgamem_size_mb > 256) {
qxl->vgamem_size_mb = 256; qxl->vgamem_size_mb = 256;
} }
qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024; qxl->vgamem_size = qxl->vgamem_size_mb * MiB;
/* vga ram (bar 0, total) */ /* vga ram (bar 0, total) */
if (qxl->ram_size_mb != -1) { if (qxl->ram_size_mb != -1) {
qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024; qxl->vga.vram_size = qxl->ram_size_mb * MiB;
} }
if (qxl->vga.vram_size < qxl->vgamem_size * 2) { if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
qxl->vga.vram_size = qxl->vgamem_size * 2; qxl->vga.vram_size = qxl->vgamem_size * 2;
@ -2024,7 +2025,7 @@ static void qxl_init_ramsize(PCIQXLDevice *qxl)
/* vram32 (surfaces, 32bit, bar 1) */ /* vram32 (surfaces, 32bit, bar 1) */
if (qxl->vram32_size_mb != -1) { if (qxl->vram32_size_mb != -1) {
qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024; qxl->vram32_size = qxl->vram32_size_mb * MiB;
} }
if (qxl->vram32_size < 4096) { if (qxl->vram32_size < 4096) {
qxl->vram32_size = 4096; qxl->vram32_size = 4096;
@ -2032,7 +2033,7 @@ static void qxl_init_ramsize(PCIQXLDevice *qxl)
/* vram (surfaces, 64bit, bar 4+5) */ /* vram (surfaces, 64bit, bar 4+5) */
if (qxl->vram_size_mb != -1) { if (qxl->vram_size_mb != -1) {
qxl->vram_size = (uint64_t)qxl->vram_size_mb * 1024 * 1024; qxl->vram_size = (uint64_t)qxl->vram_size_mb * MiB;
} }
if (qxl->vram_size < qxl->vram32_size) { if (qxl->vram_size < qxl->vram32_size) {
qxl->vram_size = qxl->vram32_size; qxl->vram_size = qxl->vram32_size;
@ -2134,13 +2135,12 @@ static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp)
} }
/* print pci bar details */ /* print pci bar details */
dprint(qxl, 1, "ram/%s: %d MB [region 0]\n", dprint(qxl, 1, "ram/%s: %" PRId64 " MB [region 0]\n",
qxl->id == 0 ? "pri" : "sec", qxl->id == 0 ? "pri" : "sec", qxl->vga.vram_size / MiB);
qxl->vga.vram_size / (1024*1024)); dprint(qxl, 1, "vram/32: %" PRIx64 " MB [region 1]\n",
dprint(qxl, 1, "vram/32: %" PRIx64 "d MB [region 1]\n", qxl->vram32_size / MiB);
qxl->vram32_size / (1024*1024)); dprint(qxl, 1, "vram/64: %" PRIx64 " MB %s\n",
dprint(qxl, 1, "vram/64: %" PRIx64 "d MB %s\n", qxl->vram_size / MiB,
qxl->vram_size / (1024*1024),
qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]"); qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
qxl->ssd.qxl.base.sif = &qxl_interface.base; qxl->ssd.qxl.base.sif = &qxl_interface.base;
@ -2167,7 +2167,7 @@ static void qxl_realize_primary(PCIDevice *dev, Error **errp)
qxl->id = 0; qxl->id = 0;
qxl_init_ramsize(qxl); qxl_init_ramsize(qxl);
vga->vbe_size = qxl->vgamem_size; vga->vbe_size = qxl->vgamem_size;
vga->vram_size_mb = qxl->vga.vram_size >> 20; vga->vram_size_mb = qxl->vga.vram_size / MiB;
vga_common_init(vga, OBJECT(dev), true); vga_common_init(vga, OBJECT(dev), true);
vga_init(vga, OBJECT(dev), vga_init(vga, OBJECT(dev),
pci_address_space(dev), pci_address_space_io(dev), false); pci_address_space(dev), pci_address_space_io(dev), false);
@ -2391,10 +2391,8 @@ static VMStateDescription qxl_vmstate = {
}; };
static Property qxl_properties[] = { static Property qxl_properties[] = {
DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * MiB),
64 * 1024 * 1024), DEFINE_PROP_UINT64("vram_size", PCIQXLDevice, vram32_size, 64 * MiB),
DEFINE_PROP_UINT64("vram_size", PCIQXLDevice, vram32_size,
64 * 1024 * 1024),
DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
QXL_DEFAULT_REVISION), QXL_DEFAULT_REVISION),
DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0), DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),

16
hw/display/sm501.c
View File

@ -24,7 +24,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/cutils.h" #include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "cpu.h" #include "cpu.h"
@ -452,12 +452,12 @@
/* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */ /* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */
static const uint32_t sm501_mem_local_size[] = { static const uint32_t sm501_mem_local_size[] = {
[0] = 4 * M_BYTE, [0] = 4 * MiB,
[1] = 8 * M_BYTE, [1] = 8 * MiB,
[2] = 16 * M_BYTE, [2] = 16 * MiB,
[3] = 32 * M_BYTE, [3] = 32 * MiB,
[4] = 64 * M_BYTE, [4] = 64 * MiB,
[5] = 2 * M_BYTE, [5] = 2 * MiB,
}; };
#define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index] #define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index]
@ -1829,7 +1829,7 @@ static void sm501_realize_pci(PCIDevice *dev, Error **errp)
} }
static Property sm501_pci_properties[] = { static Property sm501_pci_properties[] = {
DEFINE_PROP_UINT32("vram-size", SM501PCIState, vram_size, 64 * M_BYTE), DEFINE_PROP_UINT32("vram-size", SM501PCIState, vram_size, 64 * MiB),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),
}; };

5
hw/display/vga-isa-mm.c
View File

@ -22,12 +22,13 @@
* THE SOFTWARE. * THE SOFTWARE.
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "hw/display/vga.h" #include "hw/display/vga.h"
#include "vga_int.h" #include "vga_int.h"
#include "ui/pixel_ops.h" #include "ui/pixel_ops.h"
#define VGA_RAM_SIZE (8192 * 1024) #define VGA_RAM_SIZE (8 * MiB)
typedef struct ISAVGAMMState { typedef struct ISAVGAMMState {
VGACommonState vga; VGACommonState vga;
@ -130,7 +131,7 @@ int isa_vga_mm_init(hwaddr vram_base,
s = g_malloc0(sizeof(*s)); s = g_malloc0(sizeof(*s));
s->vga.vram_size_mb = VGA_RAM_SIZE >> 20; s->vga.vram_size_mb = VGA_RAM_SIZE / MiB;
vga_common_init(&s->vga, NULL, true); vga_common_init(&s->vga, NULL, true);
vga_mm_init(s, vram_base, ctrl_base, it_shift, address_space); vga_mm_init(s, vram_base, ctrl_base, it_shift, address_space);

5
hw/display/vga.c
View File

@ -22,6 +22,7 @@
* THE SOFTWARE. * THE SOFTWARE.
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "hw/display/vga.h" #include "hw/display/vga.h"
@ -721,7 +722,7 @@ uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
val = s->vbe_regs[s->vbe_index]; val = s->vbe_regs[s->vbe_index];
} }
} else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) { } else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) {
val = s->vbe_size / (64 * 1024); val = s->vbe_size / (64 * KiB);
} else { } else {
val = 0; val = 0;
} }
@ -2192,7 +2193,7 @@ void vga_common_init(VGACommonState *s, Object *obj, bool global_vmstate)
s->vram_size_mb = uint_clamp(s->vram_size_mb, 1, 512); s->vram_size_mb = uint_clamp(s->vram_size_mb, 1, 512);
s->vram_size_mb = pow2ceil(s->vram_size_mb); s->vram_size_mb = pow2ceil(s->vram_size_mb);
s->vram_size = s->vram_size_mb << 20; s->vram_size = s->vram_size_mb * MiB;
if (!s->vbe_size) { if (!s->vbe_size) {
s->vbe_size = s->vram_size; s->vbe_size = s->vram_size;

4
hw/display/virtio-gpu.c
View File

@ -12,6 +12,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "qemu/iov.h" #include "qemu/iov.h"
#include "ui/console.h" #include "ui/console.h"
@ -1314,8 +1315,7 @@ static const VMStateDescription vmstate_virtio_gpu = {
static Property virtio_gpu_properties[] = { static Property virtio_gpu_properties[] = {
DEFINE_PROP_UINT32("max_outputs", VirtIOGPU, conf.max_outputs, 1), DEFINE_PROP_UINT32("max_outputs", VirtIOGPU, conf.max_outputs, 1),
DEFINE_PROP_SIZE("max_hostmem", VirtIOGPU, conf.max_hostmem, DEFINE_PROP_SIZE("max_hostmem", VirtIOGPU, conf.max_hostmem, 256 * MiB),
256 * 1024 * 1024),
#ifdef CONFIG_VIRGL #ifdef CONFIG_VIRGL
DEFINE_PROP_BIT("virgl", VirtIOGPU, conf.flags, DEFINE_PROP_BIT("virgl", VirtIOGPU, conf.flags,
VIRTIO_GPU_FLAG_VIRGL_ENABLED, true), VIRTIO_GPU_FLAG_VIRGL_ENABLED, true),

3
hw/display/vmware_vga.c
View File

@ -22,6 +22,7 @@
* THE SOFTWARE. * THE SOFTWARE.
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "hw/loader.h" #include "hw/loader.h"
@ -565,7 +566,7 @@ static inline int vmsvga_fifo_length(struct vmsvga_state_s *s)
s->fifo_next >= SVGA_FIFO_SIZE) { s->fifo_next >= SVGA_FIFO_SIZE) {
return 0; return 0;
} }
if (s->fifo_max < s->fifo_min + 10 * 1024) { if (s->fifo_max < s->fifo_min + 10 * KiB) {
return 0; return 0;
} }

3
hw/display/xenfb.c
View File

@ -25,6 +25,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "ui/input.h" #include "ui/input.h"
@ -889,7 +890,7 @@ static int fb_initialise(struct XenDevice *xendev)
return rc; return rc;
fb_page = fb->c.page; fb_page = fb->c.page;
rc = xenfb_configure_fb(fb, videoram * 1024 * 1024U, rc = xenfb_configure_fb(fb, videoram * MiB,
fb_page->width, fb_page->height, fb_page->depth, fb_page->width, fb_page->height, fb_page->depth,
fb_page->mem_length, 0, fb_page->line_length); fb_page->mem_length, 0, fb_page->line_length);
if (rc != 0) if (rc != 0)

3
hw/hppa/dino.c
View File

@ -11,6 +11,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "cpu.h" #include "cpu.h"
#include "hw/hw.h" #include "hw/hw.h"
@ -76,7 +77,7 @@
/* #define xxx 0x200 - bit 9 not used */ /* #define xxx 0x200 - bit 9 not used */
#define RS232INT 0x400 #define RS232INT 0x400
#define DINO_MEM_CHUNK_SIZE (8 * 1024 * 1024) /* 8MB */ #define DINO_MEM_CHUNK_SIZE (8 * MiB)
#define DINO_PCI_HOST_BRIDGE(obj) \ #define DINO_PCI_HOST_BRIDGE(obj) \
OBJECT_CHECK(DinoState, (obj), TYPE_DINO_PCI_HOST_BRIDGE) OBJECT_CHECK(DinoState, (obj), TYPE_DINO_PCI_HOST_BRIDGE)

12
hw/hppa/machine.c
View File

@ -17,7 +17,7 @@
#include "hw/timer/i8254.h" #include "hw/timer/i8254.h"
#include "hw/char/serial.h" #include "hw/char/serial.h"
#include "hppa_sys.h" #include "hppa_sys.h"
#include "qemu/cutils.h" #include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu/log.h" #include "qemu/log.h"
@ -178,8 +178,8 @@ static void machine_hppa_init(MachineState *machine)
} }
qemu_log_mask(CPU_LOG_PAGE, "Kernel loaded at 0x%08" PRIx64 qemu_log_mask(CPU_LOG_PAGE, "Kernel loaded at 0x%08" PRIx64
"-0x%08" PRIx64 ", entry at 0x%08" PRIx64 "-0x%08" PRIx64 ", entry at 0x%08" PRIx64
", size %ld kB.\n", ", size %" PRIu64 " kB\n",
kernel_low, kernel_high, kernel_entry, size / 1024); kernel_low, kernel_high, kernel_entry, size / KiB);
if (kernel_cmdline) { if (kernel_cmdline) {
cpu[0]->env.gr[24] = 0x4000; cpu[0]->env.gr[24] = 0x4000;
@ -203,8 +203,8 @@ static void machine_hppa_init(MachineState *machine)
(1) Due to sign-extension problems and PDC, (1) Due to sign-extension problems and PDC,
put the initrd no higher than 1G. put the initrd no higher than 1G.
(2) Reserve 64k for stack. */ (2) Reserve 64k for stack. */
initrd_base = MIN(ram_size, 1024 * 1024 * 1024); initrd_base = MIN(ram_size, 1 * GiB);
initrd_base = initrd_base - 64 * 1024; initrd_base = initrd_base - 64 * KiB;
initrd_base = (initrd_base - initrd_size) & TARGET_PAGE_MASK; initrd_base = (initrd_base - initrd_size) & TARGET_PAGE_MASK;
if (initrd_base < kernel_high) { if (initrd_base < kernel_high) {
@ -275,7 +275,7 @@ static void machine_hppa_machine_init(MachineClass *mc)
mc->max_cpus = HPPA_MAX_CPUS; mc->max_cpus = HPPA_MAX_CPUS;
mc->default_cpus = 1; mc->default_cpus = 1;
mc->is_default = 1; mc->is_default = 1;
mc->default_ram_size = 512 * M_BYTE; mc->default_ram_size = 512 * MiB;
mc->default_boot_order = "cd"; mc->default_boot_order = "cd";
} }

4
hw/i386/acpi-build.c
View File

@ -2248,8 +2248,8 @@ build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
(void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL); (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
} }
#define HOLE_640K_START (640 * 1024) #define HOLE_640K_START (640 * KiB)
#define HOLE_640K_END (1024 * 1024) #define HOLE_640K_END (1 * MiB)
static void build_srat_hotpluggable_memory(GArray *table_data, uint64_t base, static void build_srat_hotpluggable_memory(GArray *table_data, uint64_t base,
uint64_t len, int default_node) uint64_t len, int default_node)

23
hw/i386/pc.c
View File

@ -23,6 +23,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "hw/i386/pc.h" #include "hw/i386/pc.h"
#include "hw/char/serial.h" #include "hw/char/serial.h"
@ -448,12 +449,12 @@ void pc_cmos_init(PCMachineState *pcms,
/* memory size */ /* memory size */
/* base memory (first MiB) */ /* base memory (first MiB) */
val = MIN(pcms->below_4g_mem_size / 1024, 640); val = MIN(pcms->below_4g_mem_size / KiB, 640);
rtc_set_memory(s, 0x15, val); rtc_set_memory(s, 0x15, val);
rtc_set_memory(s, 0x16, val >> 8); rtc_set_memory(s, 0x16, val >> 8);
/* extended memory (next 64MiB) */ /* extended memory (next 64MiB) */
if (pcms->below_4g_mem_size > 1024 * 1024) { if (pcms->below_4g_mem_size > 1 * MiB) {
val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024; val = (pcms->below_4g_mem_size - 1 * MiB) / KiB;
} else { } else {
val = 0; val = 0;
} }
@ -464,8 +465,8 @@ void pc_cmos_init(PCMachineState *pcms,
rtc_set_memory(s, 0x30, val); rtc_set_memory(s, 0x30, val);
rtc_set_memory(s, 0x31, val >> 8); rtc_set_memory(s, 0x31, val >> 8);
/* memory between 16MiB and 4GiB */ /* memory between 16MiB and 4GiB */
if (pcms->below_4g_mem_size > 16 * 1024 * 1024) { if (pcms->below_4g_mem_size > 16 * MiB) {
val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536; val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
} else { } else {
val = 0; val = 0;
} }
@ -1392,11 +1393,11 @@ void pc_memory_init(PCMachineState *pcms,
} }
machine->device_memory->base = machine->device_memory->base =
ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30); ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB);
if (pcmc->enforce_aligned_dimm) { if (pcmc->enforce_aligned_dimm) {
/* size device region assuming 1G page max alignment per slot */ /* size device region assuming 1G page max alignment per slot */
device_mem_size += (1ULL << 30) * machine->ram_slots; device_mem_size += (1 * GiB) * machine->ram_slots;
} }
if ((machine->device_memory->base + device_mem_size) < if ((machine->device_memory->base + device_mem_size) <
@ -1438,7 +1439,7 @@ void pc_memory_init(PCMachineState *pcms,
if (!pcmc->broken_reserved_end) { if (!pcmc->broken_reserved_end) {
res_mem_end += memory_region_size(&machine->device_memory->mr); res_mem_end += memory_region_size(&machine->device_memory->mr);
} }
*val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30)); *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
} }
@ -1475,7 +1476,7 @@ uint64_t pc_pci_hole64_start(void)
hole64_start = 0x100000000ULL + pcms->above_4g_mem_size; hole64_start = 0x100000000ULL + pcms->above_4g_mem_size;
} }
return ROUND_UP(hole64_start, 1ULL << 30); return ROUND_UP(hole64_start, 1 * GiB);
} }
qemu_irq pc_allocate_cpu_irq(void) qemu_irq pc_allocate_cpu_irq(void)
@ -2095,7 +2096,7 @@ static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
error_propagate(errp, error); error_propagate(errp, error);
return; return;
} }
if (value > (1ULL << 32)) { if (value > 4 * GiB) {
error_setg(&error, error_setg(&error,
"Machine option 'max-ram-below-4g=%"PRIu64 "Machine option 'max-ram-below-4g=%"PRIu64
"' expects size less than or equal to 4G", value); "' expects size less than or equal to 4G", value);
@ -2103,7 +2104,7 @@ static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
return; return;
} }
if (value < (1ULL << 20)) { if (value < 1 * MiB) {
warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
"BIOS may not work with less than 1MiB", value); "BIOS may not work with less than 1MiB", value);
} }

3
hw/i386/pc_piix.c
View File

@ -24,6 +24,7 @@
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "hw/loader.h" #include "hw/loader.h"
#include "hw/i386/pc.h" #include "hw/i386/pc.h"
@ -131,7 +132,7 @@ static void pc_init1(MachineState *machine,
if (lowmem > 0xc0000000) { if (lowmem > 0xc0000000) {
lowmem = 0xc0000000; lowmem = 0xc0000000;
} }
if (lowmem & ((1ULL << 30) - 1)) { if (lowmem & (1 * GiB - 1)) {
warn_report("Large machine and max_ram_below_4g " warn_report("Large machine and max_ram_below_4g "
"(%" PRIu64 ") not a multiple of 1G; " "(%" PRIu64 ") not a multiple of 1G; "
"possible bad performance.", "possible bad performance.",

3
hw/i386/pc_q35.c
View File

@ -29,6 +29,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "hw/loader.h" #include "hw/loader.h"
#include "sysemu/arch_init.h" #include "sysemu/arch_init.h"
@ -105,7 +106,7 @@ static void pc_q35_init(MachineState *machine)
if (lowmem > pcms->max_ram_below_4g) { if (lowmem > pcms->max_ram_below_4g) {
lowmem = pcms->max_ram_below_4g; lowmem = pcms->max_ram_below_4g;
if (machine->ram_size - lowmem > lowmem && if (machine->ram_size - lowmem > lowmem &&
lowmem & ((1ULL << 30) - 1)) { lowmem & (1 * GiB - 1)) {
warn_report("There is possibly poor performance as the ram size " warn_report("There is possibly poor performance as the ram size "
" (0x%" PRIx64 ") is more then twice the size of" " (0x%" PRIx64 ") is more then twice the size of"
" max-ram-below-4g (%"PRIu64") and" " max-ram-below-4g (%"PRIu64") and"

10
hw/i386/pc_sysfw.c
View File

@ -28,6 +28,7 @@
#include "sysemu/block-backend.h" #include "sysemu/block-backend.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
#include "qemu/option.h" #include "qemu/option.h"
#include "qemu/units.h"
#include "hw/sysbus.h" #include "hw/sysbus.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "hw/i386/pc.h" #include "hw/i386/pc.h"
@ -56,7 +57,7 @@ static void pc_isa_bios_init(MemoryRegion *rom_memory,
flash_size = memory_region_size(flash_mem); flash_size = memory_region_size(flash_mem);
/* map the last 128KB of the BIOS in ISA space */ /* map the last 128KB of the BIOS in ISA space */
isa_bios_size = MIN(flash_size, 128 * 1024); isa_bios_size = MIN(flash_size, 128 * KiB);
isa_bios = g_malloc(sizeof(*isa_bios)); isa_bios = g_malloc(sizeof(*isa_bios));
memory_region_init_ram(isa_bios, NULL, "isa-bios", isa_bios_size, memory_region_init_ram(isa_bios, NULL, "isa-bios", isa_bios_size,
&error_fatal); &error_fatal);
@ -83,7 +84,7 @@ static void pc_isa_bios_init(MemoryRegion *rom_memory,
* only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in
* size. * size.
*/ */
#define FLASH_MAP_BASE_MIN ((hwaddr)(0x100000000ULL - 8*1024*1024)) #define FLASH_MAP_BASE_MIN ((hwaddr)(4 * GiB - 8 * MiB))
/* This function maps flash drives from 4G downward, in order of their unit /* This function maps flash drives from 4G downward, in order of their unit
* numbers. The mapping starts at unit#0, with unit number increments of 1, and * numbers. The mapping starts at unit#0, with unit number increments of 1, and
@ -221,10 +222,7 @@ static void old_pc_system_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw)
g_free(filename); g_free(filename);
/* map the last 128KB of the BIOS in ISA space */ /* map the last 128KB of the BIOS in ISA space */
isa_bios_size = bios_size; isa_bios_size = MIN(bios_size, 128 * KiB);
if (isa_bios_size > (128 * 1024)) {
isa_bios_size = 128 * 1024;
}
isa_bios = g_malloc(sizeof(*isa_bios)); isa_bios = g_malloc(sizeof(*isa_bios));
memory_region_init_alias(isa_bios, NULL, "isa-bios", bios, memory_region_init_alias(isa_bios, NULL, "isa-bios", bios,
bios_size - isa_bios_size, isa_bios_size); bios_size - isa_bios_size, isa_bios_size);

3
hw/i386/xen/xen-mapcache.c
View File

@ -9,6 +9,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
#include <sys/resource.h> #include <sys/resource.h>
@ -46,7 +47,7 @@
* From empirical tests I observed that qemu use 75MB more than the * From empirical tests I observed that qemu use 75MB more than the
* max_mcache_size. * max_mcache_size.
*/ */
#define NON_MCACHE_MEMORY_SIZE (80 * 1024 * 1024) #define NON_MCACHE_MEMORY_SIZE (80 * MiB)
typedef struct MapCacheEntry { typedef struct MapCacheEntry {
hwaddr paddr_index; hwaddr paddr_index;

5
hw/ipack/tpci200.c
View File

@ -9,6 +9,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/ipack/ipack.h" #include "hw/ipack/ipack.h"
#include "hw/pci/pci.h" #include "hw/pci/pci.h"
#include "qemu/bitops.h" #include "qemu/bitops.h"
@ -597,9 +598,9 @@ static void tpci200_realize(PCIDevice *pci_dev, Error **errp)
memory_region_init_io(&s->las1, OBJECT(s), &tpci200_las1_ops, memory_region_init_io(&s->las1, OBJECT(s), &tpci200_las1_ops,
s, "tpci200_las1", 1024); s, "tpci200_las1", 1024);
memory_region_init_io(&s->las2, OBJECT(s), &tpci200_las2_ops, memory_region_init_io(&s->las2, OBJECT(s), &tpci200_las2_ops,
s, "tpci200_las2", 1024*1024*32); s, "tpci200_las2", 32 * MiB);
memory_region_init_io(&s->las3, OBJECT(s), &tpci200_las3_ops, memory_region_init_io(&s->las3, OBJECT(s), &tpci200_las3_ops,
s, "tpci200_las3", 1024*1024*16); s, "tpci200_las3", 16 * MiB);
pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio); pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio);
pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io); pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
pci_register_bar(&s->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las0); pci_register_bar(&s->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las0);

13
hw/lm32/lm32_boards.c
View File

@ -18,6 +18,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "cpu.h" #include "cpu.h"
@ -87,10 +88,10 @@ static void lm32_evr_init(MachineState *machine)
/* memory map */ /* memory map */
hwaddr flash_base = 0x04000000; hwaddr flash_base = 0x04000000;
size_t flash_sector_size = 256 * 1024; size_t flash_sector_size = 256 * KiB;
size_t flash_size = 32 * 1024 * 1024; size_t flash_size = 32 * MiB;
hwaddr ram_base = 0x08000000; hwaddr ram_base = 0x08000000;
size_t ram_size = 64 * 1024 * 1024; size_t ram_size = 64 * MiB;
hwaddr timer0_base = 0x80002000; hwaddr timer0_base = 0x80002000;
hwaddr uart0_base = 0x80006000; hwaddr uart0_base = 0x80006000;
hwaddr timer1_base = 0x8000a000; hwaddr timer1_base = 0x8000a000;
@ -173,10 +174,10 @@ static void lm32_uclinux_init(MachineState *machine)
/* memory map */ /* memory map */
hwaddr flash_base = 0x04000000; hwaddr flash_base = 0x04000000;
size_t flash_sector_size = 256 * 1024; size_t flash_sector_size = 256 * KiB;
size_t flash_size = 32 * 1024 * 1024; size_t flash_size = 32 * MiB;
hwaddr ram_base = 0x08000000; hwaddr ram_base = 0x08000000;
size_t ram_size = 64 * 1024 * 1024; size_t ram_size = 64 * MiB;
hwaddr uart0_base = 0x80000000; hwaddr uart0_base = 0x80000000;
hwaddr timer0_base = 0x80002000; hwaddr timer0_base = 0x80002000;
hwaddr timer1_base = 0x80010000; hwaddr timer1_base = 0x80010000;

10
hw/lm32/milkymist.c
View File

@ -18,6 +18,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "cpu.h" #include "cpu.h"
@ -33,11 +34,10 @@
#include "milkymist-hw.h" #include "milkymist-hw.h"
#include "lm32.h" #include "lm32.h"
#include "exec/address-spaces.h" #include "exec/address-spaces.h"
#include "qemu/cutils.h"
#define BIOS_FILENAME "mmone-bios.bin" #define BIOS_FILENAME "mmone-bios.bin"
#define BIOS_OFFSET 0x00860000 #define BIOS_OFFSET 0x00860000
#define BIOS_SIZE (512*1024) #define BIOS_SIZE (512 * KiB)
#define KERNEL_LOAD_ADDR 0x40000000 #define KERNEL_LOAD_ADDR 0x40000000
typedef struct { typedef struct {
@ -96,10 +96,10 @@ milkymist_init(MachineState *machine)
/* memory map */ /* memory map */
hwaddr flash_base = 0x00000000; hwaddr flash_base = 0x00000000;
size_t flash_sector_size = 128 * 1024; size_t flash_sector_size = 128 * KiB;
size_t flash_size = 32 * 1024 * 1024; size_t flash_size = 32 * MiB;
hwaddr sdram_base = 0x40000000; hwaddr sdram_base = 0x40000000;
size_t sdram_size = 128 * 1024 * 1024; size_t sdram_size = 128 * MiB;
hwaddr initrd_base = sdram_base + 0x1002000; hwaddr initrd_base = sdram_base + 0x1002000;
hwaddr cmdline_base = sdram_base + 0x1000000; hwaddr cmdline_base = sdram_base + 0x1000000;

3
hw/m68k/mcf5208.c
View File

@ -6,6 +6,7 @@
* This code is licensed under the GPL * This code is licensed under the GPL
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu-common.h" #include "qemu-common.h"
@ -241,7 +242,7 @@ static void mcf5208evb_init(MachineState *machine)
memory_region_add_subregion(address_space_mem, 0x40000000, ram); memory_region_add_subregion(address_space_mem, 0x40000000, ram);
/* Internal SRAM. */ /* Internal SRAM. */
memory_region_init_ram(sram, NULL, "mcf5208.sram", 16384, &error_fatal); memory_region_init_ram(sram, NULL, "mcf5208.sram", 16 * KiB, &error_fatal);
memory_region_add_subregion(address_space_mem, 0x80000000, sram); memory_region_add_subregion(address_space_mem, 0x80000000, sram);
/* Internal peripherals. */ /* Internal peripherals. */

7
hw/microblaze/petalogix_ml605_mmu.c
View File

@ -26,6 +26,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "cpu.h" #include "cpu.h"
@ -44,8 +45,8 @@
#include "hw/stream.h" #include "hw/stream.h"
#define LMB_BRAM_SIZE (128 * 1024) #define LMB_BRAM_SIZE (128 * KiB)
#define FLASH_SIZE (32 * 1024 * 1024) #define FLASH_SIZE (32 * MiB)
#define BINARY_DEVICE_TREE_FILE "petalogix-ml605.dtb" #define BINARY_DEVICE_TREE_FILE "petalogix-ml605.dtb"
@ -109,7 +110,7 @@ petalogix_ml605_init(MachineState *machine)
pflash_cfi01_register(FLASH_BASEADDR, pflash_cfi01_register(FLASH_BASEADDR,
NULL, "petalogix_ml605.flash", FLASH_SIZE, NULL, "petalogix_ml605.flash", FLASH_SIZE,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
(64 * 1024), FLASH_SIZE >> 16, 64 * KiB, FLASH_SIZE >> 16,
2, 0x89, 0x18, 0x0000, 0x0, 0); 2, 0x89, 0x18, 0x0000, 0x0, 0);

7
hw/microblaze/petalogix_s3adsp1800_mmu.c
View File

@ -24,6 +24,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "cpu.h" #include "cpu.h"
@ -39,8 +40,8 @@
#include "boot.h" #include "boot.h"
#define LMB_BRAM_SIZE (128 * 1024) #define LMB_BRAM_SIZE (128 * KiB)
#define FLASH_SIZE (16 * 1024 * 1024) #define FLASH_SIZE (16 * MiB)
#define BINARY_DEVICE_TREE_FILE "petalogix-s3adsp1800.dtb" #define BINARY_DEVICE_TREE_FILE "petalogix-s3adsp1800.dtb"
@ -87,7 +88,7 @@ petalogix_s3adsp1800_init(MachineState *machine)
pflash_cfi01_register(FLASH_BASEADDR, pflash_cfi01_register(FLASH_BASEADDR,
NULL, "petalogix_s3adsp1800.flash", FLASH_SIZE, NULL, "petalogix_s3adsp1800.flash", FLASH_SIZE,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
(64 * 1024), FLASH_SIZE >> 16, 64 * KiB, FLASH_SIZE >> 16,
1, 0x89, 0x18, 0x0000, 0x0, 1); 1, 0x89, 0x18, 0x0000, 0x0, 1);
dev = qdev_create(NULL, "xlnx.xps-intc"); dev = qdev_create(NULL, "xlnx.xps-intc");

30
hw/mips/boston.c
View File

@ -18,6 +18,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "exec/address-spaces.h" #include "exec/address-spaces.h"
@ -32,7 +33,6 @@
#include "hw/mips/cpudevs.h" #include "hw/mips/cpudevs.h"
#include "hw/pci-host/xilinx-pcie.h" #include "hw/pci-host/xilinx-pcie.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu/cutils.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
#include "qemu/log.h" #include "qemu/log.h"
#include "chardev/char.h" #include "chardev/char.h"
@ -200,7 +200,7 @@ static uint64_t boston_platreg_read(void *opaque, hwaddr addr,
val |= PLAT_BUILD_CFG_PCIE2_EN; val |= PLAT_BUILD_CFG_PCIE2_EN;
return val; return val;
case PLAT_DDR_CFG: case PLAT_DDR_CFG:
val = s->mach->ram_size / G_BYTE; val = s->mach->ram_size / GiB;
assert(!(val & ~PLAT_DDR_CFG_SIZE)); assert(!(val & ~PLAT_DDR_CFG_SIZE));
val |= PLAT_DDR_CFG_MHZ; val |= PLAT_DDR_CFG_MHZ;
return val; return val;
@ -355,7 +355,7 @@ static const void *boston_fdt_filter(void *opaque, const void *fdt_orig,
return NULL; return NULL;
} }
ram_low_sz = MIN(256 * M_BYTE, machine->ram_size); ram_low_sz = MIN(256 * MiB, machine->ram_size);
ram_high_sz = machine->ram_size - ram_low_sz; ram_high_sz = machine->ram_size - ram_low_sz;
qemu_fdt_setprop_sized_cells(fdt, "/memory@0", "reg", qemu_fdt_setprop_sized_cells(fdt, "/memory@0", "reg",
1, 0x00000000, 1, ram_low_sz, 1, 0x00000000, 1, ram_low_sz,
@ -436,8 +436,8 @@ static void boston_mach_init(MachineState *machine)
int fw_size, fit_err; int fw_size, fit_err;
bool is_64b; bool is_64b;
if ((machine->ram_size % G_BYTE) || if ((machine->ram_size % GiB) ||
(machine->ram_size > (2 * G_BYTE))) { (machine->ram_size > (2 * GiB))) {
error_report("Memory size must be 1GB or 2GB"); error_report("Memory size must be 1GB or 2GB");
exit(1); exit(1);
} }
@ -471,7 +471,7 @@ static void boston_mach_init(MachineState *machine)
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1); sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1);
flash = g_new(MemoryRegion, 1); flash = g_new(MemoryRegion, 1);
memory_region_init_rom(flash, NULL, "boston.flash", 128 * M_BYTE, &err); memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB, &err);
memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0); memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0);
ddr = g_new(MemoryRegion, 1); ddr = g_new(MemoryRegion, 1);
@ -481,22 +481,22 @@ static void boston_mach_init(MachineState *machine)
ddr_low_alias = g_new(MemoryRegion, 1); ddr_low_alias = g_new(MemoryRegion, 1);
memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr", memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr",
ddr, 0, MIN(machine->ram_size, (256 * M_BYTE))); ddr, 0, MIN(machine->ram_size, (256 * MiB)));
memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0); memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0);
xilinx_pcie_init(sys_mem, 0, xilinx_pcie_init(sys_mem, 0,
0x10000000, 32 * M_BYTE, 0x10000000, 32 * MiB,
0x40000000, 1 * G_BYTE, 0x40000000, 1 * GiB,
get_cps_irq(s->cps, 2), false); get_cps_irq(s->cps, 2), false);
xilinx_pcie_init(sys_mem, 1, xilinx_pcie_init(sys_mem, 1,
0x12000000, 32 * M_BYTE, 0x12000000, 32 * MiB,
0x20000000, 512 * M_BYTE, 0x20000000, 512 * MiB,
get_cps_irq(s->cps, 1), false); get_cps_irq(s->cps, 1), false);
pcie2 = xilinx_pcie_init(sys_mem, 2, pcie2 = xilinx_pcie_init(sys_mem, 2,
0x14000000, 32 * M_BYTE, 0x14000000, 32 * MiB,
0x16000000, 1 * M_BYTE, 0x16000000, 1 * MiB,
get_cps_irq(s->cps, 0), true); get_cps_irq(s->cps, 0), true);
platreg = g_new(MemoryRegion, 1); platreg = g_new(MemoryRegion, 1);
@ -526,7 +526,7 @@ static void boston_mach_init(MachineState *machine)
if (machine->firmware) { if (machine->firmware) {
fw_size = load_image_targphys(machine->firmware, fw_size = load_image_targphys(machine->firmware,
0x1fc00000, 4 * M_BYTE); 0x1fc00000, 4 * MiB);
if (fw_size == -1) { if (fw_size == -1) {
error_printf("unable to load firmware image '%s'\n", error_printf("unable to load firmware image '%s'\n",
machine->firmware); machine->firmware);
@ -552,7 +552,7 @@ static void boston_mach_class_init(MachineClass *mc)
mc->desc = "MIPS Boston"; mc->desc = "MIPS Boston";
mc->init = boston_mach_init; mc->init = boston_mach_init;
mc->block_default_type = IF_IDE; mc->block_default_type = IF_IDE;
mc->default_ram_size = 1 * G_BYTE; mc->default_ram_size = 1 * GiB;
mc->max_cpus = 16; mc->max_cpus = 16;
mc->default_cpu_type = MIPS_CPU_TYPE_NAME("I6400"); mc->default_cpu_type = MIPS_CPU_TYPE_NAME("I6400");
} }

7
hw/mips/mips_fulong2e.c
View File

@ -19,6 +19,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "hw/i386/pc.h" #include "hw/i386/pc.h"
@ -159,7 +160,7 @@ static int64_t load_kernel (CPUMIPSState *env)
/* Setup minimum environment variables */ /* Setup minimum environment variables */
prom_set(prom_buf, index++, "busclock=33000000"); prom_set(prom_buf, index++, "busclock=33000000");
prom_set(prom_buf, index++, "cpuclock=100000000"); prom_set(prom_buf, index++, "cpuclock=100000000");
prom_set(prom_buf, index++, "memsize=%i", loaderparams.ram_size/1024/1024); prom_set(prom_buf, index++, "memsize=%"PRIi64, loaderparams.ram_size / MiB);
prom_set(prom_buf, index++, "modetty0=38400n8r"); prom_set(prom_buf, index++, "modetty0=38400n8r");
prom_set(prom_buf, index++, NULL); prom_set(prom_buf, index++, NULL);
@ -303,10 +304,10 @@ static void mips_fulong2e_init(MachineState *machine)
qemu_register_reset(main_cpu_reset, cpu); qemu_register_reset(main_cpu_reset, cpu);
/* fulong 2e has 256M ram. */ /* fulong 2e has 256M ram. */
ram_size = 256 * 1024 * 1024; ram_size = 256 * MiB;
/* fulong 2e has a 1M flash.Winbond W39L040AP70Z */ /* fulong 2e has a 1M flash.Winbond W39L040AP70Z */
bios_size = 1024 * 1024; bios_size = 1 * MiB;
/* allocate RAM */ /* allocate RAM */
memory_region_allocate_system_memory(ram, NULL, "fulong2e.ram", ram_size); memory_region_allocate_system_memory(ram, NULL, "fulong2e.ram", ram_size);

25
hw/mips/mips_malta.c
View File

@ -23,6 +23,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "cpu.h" #include "cpu.h"
#include "hw/hw.h" #include "hw/hw.h"
@ -191,7 +192,7 @@ static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size)
int i; int i;
/* work in terms of MB */ /* work in terms of MB */
ram_size >>= 20; ram_size /= MiB;
while ((ram_size >= 4) && (nbanks <= 2)) { while ((ram_size >= 4) && (nbanks <= 2)) {
int sz_log2 = MIN(31 - clz32(ram_size), 14); int sz_log2 = MIN(31 - clz32(ram_size), 14);
@ -843,7 +844,8 @@ static int64_t load_kernel (void)
/* The kernel allocates the bootmap memory in the low memory after /* The kernel allocates the bootmap memory in the low memory after
the initrd. It takes at most 128kiB for 2GB RAM and 4kiB the initrd. It takes at most 128kiB for 2GB RAM and 4kiB
pages. */ pages. */
initrd_offset = (loaderparams.ram_low_size - initrd_size - 131072 initrd_offset = (loaderparams.ram_low_size - initrd_size
- (128 * KiB)
- ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK; - ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK;
if (kernel_high >= initrd_offset) { if (kernel_high >= initrd_offset) {
error_report("memory too small for initial ram disk '%s'", error_report("memory too small for initial ram disk '%s'",
@ -1021,9 +1023,9 @@ void mips_malta_init(MachineState *machine)
mips_create_cpu(s, machine->cpu_type, &cbus_irq, &i8259_irq); mips_create_cpu(s, machine->cpu_type, &cbus_irq, &i8259_irq);
/* allocate RAM */ /* allocate RAM */
if (ram_size > (2048u << 20)) { if (ram_size > 2 * GiB) {
error_report("Too much memory for this machine: %dMB, maximum 2048MB", error_report("Too much memory for this machine: %" PRId64 "MB,"
((unsigned int)ram_size / (1 << 20))); " maximum 2048MB", ram_size / MiB);
exit(1); exit(1);
} }
@ -1034,17 +1036,18 @@ void mips_malta_init(MachineState *machine)
/* alias for pre IO hole access */ /* alias for pre IO hole access */
memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram", memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram",
ram_high, 0, MIN(ram_size, (256 << 20))); ram_high, 0, MIN(ram_size, 256 * MiB));
memory_region_add_subregion(system_memory, 0, ram_low_preio); memory_region_add_subregion(system_memory, 0, ram_low_preio);
/* alias for post IO hole access, if there is enough RAM */ /* alias for post IO hole access, if there is enough RAM */
if (ram_size > (512 << 20)) { if (ram_size > 512 * MiB) {
ram_low_postio = g_new(MemoryRegion, 1); ram_low_postio = g_new(MemoryRegion, 1);
memory_region_init_alias(ram_low_postio, NULL, memory_region_init_alias(ram_low_postio, NULL,
"mips_malta_low_postio.ram", "mips_malta_low_postio.ram",
ram_high, 512 << 20, ram_high, 512 * MiB,
ram_size - (512 << 20)); ram_size - 512 * MiB);
memory_region_add_subregion(system_memory, 512 << 20, ram_low_postio); memory_region_add_subregion(system_memory, 512 * MiB,
ram_low_postio);
} }
#ifdef TARGET_WORDS_BIGENDIAN #ifdef TARGET_WORDS_BIGENDIAN
@ -1076,7 +1079,7 @@ void mips_malta_init(MachineState *machine)
bios = pflash_cfi01_get_memory(fl); bios = pflash_cfi01_get_memory(fl);
fl_idx++; fl_idx++;
if (kernel_filename) { if (kernel_filename) {
ram_low_size = MIN(ram_size, 256 << 20); ram_low_size = MIN(ram_size, 256 * MiB);
/* For KVM we reserve 1MB of RAM for running bootloader */ /* For KVM we reserve 1MB of RAM for running bootloader */
if (kvm_enabled()) { if (kvm_enabled()) {
ram_low_size -= 0x100000; ram_low_size -= 0x100000;

15
hw/mips/mips_r4k.c
View File

@ -8,6 +8,7 @@
* the standard PC ISA addresses. * the standard PC ISA addresses.
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "cpu.h" #include "cpu.h"
@ -79,8 +80,9 @@ typedef struct ResetData {
static int64_t load_kernel(void) static int64_t load_kernel(void)
{ {
const size_t params_size = 264;
int64_t entry, kernel_high; int64_t entry, kernel_high;
long kernel_size, initrd_size, params_size; long kernel_size, initrd_size;
ram_addr_t initrd_offset; ram_addr_t initrd_offset;
uint32_t *params_buf; uint32_t *params_buf;
int big_endian; int big_endian;
@ -128,7 +130,6 @@ static int64_t load_kernel(void)
} }
/* Store command line. */ /* Store command line. */
params_size = 264;
params_buf = g_malloc(params_size); params_buf = g_malloc(params_size);
params_buf[0] = tswap32(ram_size); params_buf[0] = tswap32(ram_size);
@ -143,7 +144,7 @@ static int64_t load_kernel(void)
} }
rom_add_blob_fixed("params", params_buf, params_size, rom_add_blob_fixed("params", params_buf, params_size,
(16 << 20) - 264); 16 * MiB - params_size);
g_free(params_buf); g_free(params_buf);
return entry; return entry;
@ -158,7 +159,7 @@ static void main_cpu_reset(void *opaque)
env->active_tc.PC = s->vector; env->active_tc.PC = s->vector;
} }
static const int sector_len = 32 * 1024; static const int sector_len = 32 * KiB;
static static
void mips_r4k_init(MachineState *machine) void mips_r4k_init(MachineState *machine)
{ {
@ -194,9 +195,9 @@ void mips_r4k_init(MachineState *machine)
qemu_register_reset(main_cpu_reset, reset_info); qemu_register_reset(main_cpu_reset, reset_info);
/* allocate RAM */ /* allocate RAM */
if (ram_size > (256 << 20)) { if (ram_size > 256 * MiB) {
error_report("Too much memory for this machine: %dMB, maximum 256MB", error_report("Too much memory for this machine: %" PRId64 "MB,"
((unsigned int)ram_size / (1 << 20))); " maximum 256MB", ram_size / MiB);
exit(1); exit(1);
} }
memory_region_allocate_system_memory(ram, NULL, "mips_r4k.ram", ram_size); memory_region_allocate_system_memory(ram, NULL, "mips_r4k.ram", ram_size);

3
hw/misc/auxbus.c
View File

@ -27,6 +27,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/log.h" #include "qemu/log.h"
#include "hw/misc/auxbus.h" #include "hw/misc/auxbus.h"
#include "hw/i2c/i2c.h" #include "hw/i2c/i2c.h"
@ -68,7 +69,7 @@ AUXBus *aux_init_bus(DeviceState *parent, const char *name)
/* Memory related. */ /* Memory related. */
bus->aux_io = g_malloc(sizeof(*bus->aux_io)); bus->aux_io = g_malloc(sizeof(*bus->aux_io));
memory_region_init(bus->aux_io, OBJECT(bus), "aux-io", (1 << 20)); memory_region_init(bus->aux_io, OBJECT(bus), "aux-io", 1 * MiB);
address_space_init(&bus->aux_addr_space, bus->aux_io, "aux-io"); address_space_init(&bus->aux_addr_space, bus->aux_io, "aux-io");
return bus; return bus;
} }

3
hw/misc/edu.c
View File

@ -23,6 +23,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/pci/pci.h" #include "hw/pci/pci.h"
#include "hw/pci/msi.h" #include "hw/pci/msi.h"
#include "qemu/timer.h" #include "qemu/timer.h"
@ -357,7 +358,7 @@ static void pci_edu_realize(PCIDevice *pdev, Error **errp)
edu, QEMU_THREAD_JOINABLE); edu, QEMU_THREAD_JOINABLE);
memory_region_init_io(&edu->mmio, OBJECT(edu), &edu_mmio_ops, edu, memory_region_init_io(&edu->mmio, OBJECT(edu), &edu_mmio_ops, edu,
"edu-mmio", 1 << 20); "edu-mmio", 1 * MiB);
pci_register_bar(pdev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &edu->mmio); pci_register_bar(pdev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &edu->mmio);
} }

3
hw/misc/ivshmem.c
View File

@ -17,6 +17,7 @@
* GNU GPL, version 2 or (at your option) any later version. * GNU GPL, version 2 or (at your option) any later version.
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu/cutils.h" #include "qemu/cutils.h"
#include "hw/hw.h" #include "hw/hw.h"
@ -1301,7 +1302,7 @@ static void ivshmem_realize(PCIDevice *dev, Error **errp)
} }
if (s->sizearg == NULL) { if (s->sizearg == NULL) {
s->legacy_size = 4 << 20; /* 4 MB default */ s->legacy_size = 4 * MiB; /* 4 MB default */
} else { } else {
int ret; int ret;
uint64_t size; uint64_t size;

3
hw/misc/mips_itu.c
View File

@ -18,6 +18,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/log.h" #include "qemu/log.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "cpu.h" #include "cpu.h"
@ -80,7 +81,7 @@ static void itc_reconfigure(MIPSITUState *tag)
uint64_t *am = &tag->ITCAddressMap[0]; uint64_t *am = &tag->ITCAddressMap[0];
MemoryRegion *mr = &tag->storage_io; MemoryRegion *mr = &tag->storage_io;
hwaddr address = am[0] & ITC_AM0_BASE_ADDRESS_MASK; hwaddr address = am[0] & ITC_AM0_BASE_ADDRESS_MASK;
uint64_t size = (1 << 10) + (am[1] & ITC_AM1_ADDR_MASK_MASK); uint64_t size = (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK);
bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0; bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0;
memory_region_transaction_begin(); memory_region_transaction_begin();

7
hw/net/e1000e.c
View File

@ -34,6 +34,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "net/net.h" #include "net/net.h"
#include "net/tap.h" #include "net/tap.h"
#include "qemu/range.h" #include "qemu/range.h"
@ -81,10 +82,10 @@ typedef struct E1000EState {
#define E1000E_IO_IDX 2 #define E1000E_IO_IDX 2
#define E1000E_MSIX_IDX 3 #define E1000E_MSIX_IDX 3
#define E1000E_MMIO_SIZE (128 * 1024) #define E1000E_MMIO_SIZE (128 * KiB)
#define E1000E_FLASH_SIZE (128 * 1024) #define E1000E_FLASH_SIZE (128 * KiB)
#define E1000E_IO_SIZE (32) #define E1000E_IO_SIZE (32)
#define E1000E_MSIX_SIZE (16 * 1024) #define E1000E_MSIX_SIZE (16 * KiB)
#define E1000E_MSIX_TABLE (0x0000) #define E1000E_MSIX_TABLE (0x0000)
#define E1000E_MSIX_PBA (0x2000) #define E1000E_MSIX_PBA (0x2000)

3
hw/net/e1000x_common.c
View File

@ -23,6 +23,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "hw/pci/pci.h" #include "hw/pci/pci.h"
#include "net/net.h" #include "net/net.h"
@ -111,7 +112,7 @@ bool e1000x_is_oversized(uint32_t *mac, size_t size)
static const int maximum_ethernet_vlan_size = 1522; static const int maximum_ethernet_vlan_size = 1522;
/* this is the size past which hardware will /* this is the size past which hardware will
drop packets when setting LPE=1 */ drop packets when setting LPE=1 */
static const int maximum_ethernet_lpe_size = 16384; static const int maximum_ethernet_lpe_size = 16 * KiB;
if ((size > maximum_ethernet_lpe_size || if ((size > maximum_ethernet_lpe_size ||
(size > maximum_ethernet_vlan_size (size > maximum_ethernet_vlan_size

3
hw/net/eepro100.c
View File

@ -41,6 +41,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "hw/pci/pci.h" #include "hw/pci/pci.h"
#include "net/net.h" #include "net/net.h"
@ -60,8 +61,6 @@
* changed to pad short packets itself. */ * changed to pad short packets itself. */
#define CONFIG_PAD_RECEIVED_FRAMES #define CONFIG_PAD_RECEIVED_FRAMES
#define KiB 1024
/* Debug EEPRO100 card. */ /* Debug EEPRO100 card. */
#if 0 #if 0
# define DEBUG_EEPRO100 # define DEBUG_EEPRO100

5
hw/net/ne2000.h
View File

@ -1,11 +1,12 @@
#ifndef HW_NE2000_H #ifndef HW_NE2000_H
#define HW_NE2000_H #define HW_NE2000_H
#include "qemu/units.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "net/net.h" #include "net/net.h"
#define NE2000_PMEM_SIZE (32*1024) #define NE2000_PMEM_SIZE (32 * KiB)
#define NE2000_PMEM_START (16*1024) #define NE2000_PMEM_START (16 * KiB)
#define NE2000_PMEM_END (NE2000_PMEM_SIZE+NE2000_PMEM_START) #define NE2000_PMEM_END (NE2000_PMEM_SIZE+NE2000_PMEM_START)
#define NE2000_MEM_SIZE NE2000_PMEM_END #define NE2000_MEM_SIZE NE2000_PMEM_END

6
hw/nios2/boot.c
View File

@ -29,6 +29,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "cpu.h" #include "cpu.h"
#include "qemu/option.h" #include "qemu/option.h"
@ -38,7 +39,6 @@
#include "sysemu/sysemu.h" #include "sysemu/sysemu.h"
#include "hw/loader.h" #include "hw/loader.h"
#include "elf.h" #include "elf.h"
#include "qemu/cutils.h"
#include "boot.h" #include "boot.h"
@ -177,7 +177,7 @@ void nios2_load_kernel(Nios2CPU *cpu, hwaddr ddr_base,
high = ddr_base + kernel_size; high = ddr_base + kernel_size;
} }
high = ROUND_UP(high, 1024 * 1024); high = ROUND_UP(high, 1 * MiB);
/* If initrd is available, it goes after the kernel, aligned to 1M. */ /* If initrd is available, it goes after the kernel, aligned to 1M. */
if (initrd_filename) { if (initrd_filename) {
@ -213,7 +213,7 @@ void nios2_load_kernel(Nios2CPU *cpu, hwaddr ddr_base,
high += fdt_size; high += fdt_size;
/* Kernel command is at the end, 4k aligned. */ /* Kernel command is at the end, 4k aligned. */
boot_info.cmdline = ROUND_UP(high, 4096); boot_info.cmdline = ROUND_UP(high, 4 * KiB);
if (kernel_cmdline && strlen(kernel_cmdline)) { if (kernel_cmdline && strlen(kernel_cmdline)) {
pstrcpy_targphys("cmdline", boot_info.cmdline, 256, kernel_cmdline); pstrcpy_targphys("cmdline", boot_info.cmdline, 256, kernel_cmdline);
} }

11
hw/nvram/spapr_nvram.c
View File

@ -23,6 +23,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "cpu.h" #include "cpu.h"
@ -47,9 +48,9 @@ typedef struct sPAPRNVRAM {
#define VIO_SPAPR_NVRAM(obj) \ #define VIO_SPAPR_NVRAM(obj) \
OBJECT_CHECK(sPAPRNVRAM, (obj), TYPE_VIO_SPAPR_NVRAM) OBJECT_CHECK(sPAPRNVRAM, (obj), TYPE_VIO_SPAPR_NVRAM)
#define MIN_NVRAM_SIZE 8192 #define MIN_NVRAM_SIZE (8 * KiB)
#define DEFAULT_NVRAM_SIZE 65536 #define DEFAULT_NVRAM_SIZE (64 * KiB)
#define MAX_NVRAM_SIZE 1048576 #define MAX_NVRAM_SIZE (1 * MiB)
static void rtas_nvram_fetch(PowerPCCPU *cpu, sPAPRMachineState *spapr, static void rtas_nvram_fetch(PowerPCCPU *cpu, sPAPRMachineState *spapr,
uint32_t token, uint32_t nargs, uint32_t token, uint32_t nargs,
@ -167,7 +168,9 @@ static void spapr_nvram_realize(VIOsPAPRDevice *dev, Error **errp)
nvram->buf = g_malloc0(nvram->size); nvram->buf = g_malloc0(nvram->size);
if ((nvram->size < MIN_NVRAM_SIZE) || (nvram->size > MAX_NVRAM_SIZE)) { if ((nvram->size < MIN_NVRAM_SIZE) || (nvram->size > MAX_NVRAM_SIZE)) {
error_setg(errp, "spapr-nvram must be between %d and %d bytes in size", error_setg(errp,
"spapr-nvram must be between %" PRId64
" and %" PRId64 " bytes in size",
MIN_NVRAM_SIZE, MAX_NVRAM_SIZE); MIN_NVRAM_SIZE, MAX_NVRAM_SIZE);
return; return;
} }

3
hw/pci-host/prep.c
View File

@ -24,6 +24,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "hw/pci/pci.h" #include "hw/pci/pci.h"
@ -70,7 +71,7 @@ typedef struct PRePPCIState {
int contiguous_map; int contiguous_map;
} PREPPCIState; } PREPPCIState;
#define BIOS_SIZE (1024 * 1024) #define BIOS_SIZE (1 * MiB)
static inline uint32_t raven_pci_io_config(hwaddr addr) static inline uint32_t raven_pci_io_config(hwaddr addr)
{ {

5
hw/pci-host/xilinx-pcie.c
View File

@ -18,6 +18,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "hw/pci/pci_bridge.h" #include "hw/pci/pci_bridge.h"
#include "hw/pci-host/xilinx-pcie.h" #include "hw/pci-host/xilinx-pcie.h"
@ -157,9 +158,9 @@ static void xilinx_pcie_host_init(Object *obj)
static Property xilinx_pcie_host_props[] = { static Property xilinx_pcie_host_props[] = {
DEFINE_PROP_UINT32("bus_nr", XilinxPCIEHost, bus_nr, 0), DEFINE_PROP_UINT32("bus_nr", XilinxPCIEHost, bus_nr, 0),
DEFINE_PROP_SIZE("cfg_base", XilinxPCIEHost, cfg_base, 0), DEFINE_PROP_SIZE("cfg_base", XilinxPCIEHost, cfg_base, 0),
DEFINE_PROP_SIZE("cfg_size", XilinxPCIEHost, cfg_size, 32 << 20), DEFINE_PROP_SIZE("cfg_size", XilinxPCIEHost, cfg_size, 32 * MiB),
DEFINE_PROP_SIZE("mmio_base", XilinxPCIEHost, mmio_base, 0), DEFINE_PROP_SIZE("mmio_base", XilinxPCIEHost, mmio_base, 0),
DEFINE_PROP_SIZE("mmio_size", XilinxPCIEHost, mmio_size, 1 << 20), DEFINE_PROP_SIZE("mmio_size", XilinxPCIEHost, mmio_size, 1 * MiB),
DEFINE_PROP_BOOL("link_up", XilinxPCIEHost, link_up, true), DEFINE_PROP_BOOL("link_up", XilinxPCIEHost, link_up, true),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),
}; };

13
hw/ppc/e500.c
View File

@ -15,6 +15,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "e500.h" #include "e500.h"
#include "e500-ccsr.h" #include "e500-ccsr.h"
@ -46,11 +47,11 @@
#define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb"
#define DTC_LOAD_PAD 0x1800000 #define DTC_LOAD_PAD 0x1800000
#define DTC_PAD_MASK 0xFFFFF #define DTC_PAD_MASK 0xFFFFF
#define DTB_MAX_SIZE (8 * 1024 * 1024) #define DTB_MAX_SIZE (8 * MiB)
#define INITRD_LOAD_PAD 0x2000000 #define INITRD_LOAD_PAD 0x2000000
#define INITRD_PAD_MASK 0xFFFFFF #define INITRD_PAD_MASK 0xFFFFFF
#define RAM_SIZES_ALIGN (64UL << 20) #define RAM_SIZES_ALIGN (64 * MiB)
/* TODO: parameterize */ /* TODO: parameterize */
#define MPC8544_CCSRBAR_SIZE 0x00100000ULL #define MPC8544_CCSRBAR_SIZE 0x00100000ULL
@ -603,7 +604,7 @@ static int ppce500_prep_device_tree(PPCE500MachineState *machine,
/* Create -kernel TLB entries for BookE. */ /* Create -kernel TLB entries for BookE. */
hwaddr booke206_page_size_to_tlb(uint64_t size) hwaddr booke206_page_size_to_tlb(uint64_t size)
{ {
return 63 - clz64(size >> 10); return 63 - clz64(size / KiB);
} }
static int booke206_initial_map_tsize(CPUPPCState *env) static int booke206_initial_map_tsize(CPUPPCState *env)
@ -671,7 +672,7 @@ static void ppce500_cpu_reset(void *opaque)
/* Set initial guest state. */ /* Set initial guest state. */
cs->halted = 0; cs->halted = 0;
env->gpr[1] = (16<<20) - 8; env->gpr[1] = (16 * MiB) - 8;
env->gpr[3] = bi->dt_base; env->gpr[3] = bi->dt_base;
env->gpr[4] = 0; env->gpr[4] = 0;
env->gpr[5] = 0; env->gpr[5] = 0;
@ -1012,9 +1013,9 @@ void ppce500_init(MachineState *machine)
} }
cur_base = loadaddr + payload_size; cur_base = loadaddr + payload_size;
if (cur_base < (32 * 1024 * 1024)) { if (cur_base < 32 * MiB) {
/* u-boot occupies memory up to 32MB, so load blobs above */ /* u-boot occupies memory up to 32MB, so load blobs above */
cur_base = (32 * 1024 * 1024); cur_base = 32 * MiB;
} }
/* Load bare kernel only if no bios/u-boot has been provided */ /* Load bare kernel only if no bios/u-boot has been provided */

3
hw/ppc/e500plat.c
View File

@ -10,6 +10,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "e500.h" #include "e500.h"
#include "hw/net/fsl_etsec/etsec.h" #include "hw/net/fsl_etsec/etsec.h"
@ -85,7 +86,7 @@ static void e500plat_machine_class_init(ObjectClass *oc, void *data)
pmc->has_mpc8xxx_gpio = true; pmc->has_mpc8xxx_gpio = true;
pmc->has_platform_bus = true; pmc->has_platform_bus = true;
pmc->platform_bus_base = 0xf00000000ULL; pmc->platform_bus_base = 0xf00000000ULL;
pmc->platform_bus_size = (128ULL * 1024 * 1024); pmc->platform_bus_size = 128 * MiB;
pmc->platform_bus_first_irq = 5; pmc->platform_bus_first_irq = 5;
pmc->platform_bus_num_irqs = 10; pmc->platform_bus_num_irqs = 10;
pmc->ccsrbar_base = 0xFE0000000ULL; pmc->ccsrbar_base = 0xFE0000000ULL;

3
hw/ppc/mac.h
View File

@ -26,6 +26,7 @@
#ifndef PPC_MAC_H #ifndef PPC_MAC_H
#define PPC_MAC_H #define PPC_MAC_H
#include "qemu/units.h"
#include "exec/memory.h" #include "exec/memory.h"
#include "hw/boards.h" #include "hw/boards.h"
#include "hw/sysbus.h" #include "hw/sysbus.h"
@ -38,7 +39,7 @@
/* SMP is not enabled, for now */ /* SMP is not enabled, for now */
#define MAX_CPUS 1 #define MAX_CPUS 1
#define BIOS_SIZE (1024 * 1024) #define BIOS_SIZE (1 * MiB)
#define NVRAM_SIZE 0x2000 #define NVRAM_SIZE 0x2000
#define PROM_FILENAME "openbios-ppc" #define PROM_FILENAME "openbios-ppc"
#define PROM_ADDR 0xfff00000 #define PROM_ADDR 0xfff00000

1
hw/ppc/mac_newworld.c
View File

@ -71,7 +71,6 @@
#include "hw/usb.h" #include "hw/usb.h"
#include "exec/address-spaces.h" #include "exec/address-spaces.h"
#include "hw/sysbus.h" #include "hw/sysbus.h"
#include "qemu/cutils.h"
#include "trace.h" #include "trace.h"
#define MAX_IDE_BUS 2 #define MAX_IDE_BUS 2

9
hw/ppc/mac_oldworld.c
View File

@ -24,6 +24,7 @@
* THE SOFTWARE. * THE SOFTWARE.
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "hw/ppc/ppc.h" #include "hw/ppc/ppc.h"
@ -46,7 +47,6 @@
#include "sysemu/kvm.h" #include "sysemu/kvm.h"
#include "kvm_ppc.h" #include "kvm_ppc.h"
#include "exec/address-spaces.h" #include "exec/address-spaces.h"
#include "qemu/cutils.h"
#define MAX_IDE_BUS 2 #define MAX_IDE_BUS 2
#define CFG_ADDR 0xf0000510 #define CFG_ADDR 0xf0000510
@ -118,10 +118,9 @@ static void ppc_heathrow_init(MachineState *machine)
} }
/* allocate RAM */ /* allocate RAM */
if (ram_size > (2047 << 20)) { if (ram_size > 2047 * MiB) {
fprintf(stderr, error_report("Too much memory for this machine: %" PRId64 " MB, "
"qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n", "maximum 2047 MB", ram_size / MiB);
((unsigned int)ram_size / (1 << 20)));
exit(1); exit(1);
} }

6
hw/ppc/pnv.c
View File

@ -18,6 +18,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "sysemu/sysemu.h" #include "sysemu/sysemu.h"
#include "sysemu/numa.h" #include "sysemu/numa.h"
@ -31,7 +32,6 @@
#include "hw/ppc/pnv_core.h" #include "hw/ppc/pnv_core.h"
#include "hw/loader.h" #include "hw/loader.h"
#include "exec/address-spaces.h" #include "exec/address-spaces.h"
#include "qemu/cutils.h"
#include "qapi/visitor.h" #include "qapi/visitor.h"
#include "monitor/monitor.h" #include "monitor/monitor.h"
#include "hw/intc/intc.h" #include "hw/intc/intc.h"
@ -556,7 +556,7 @@ static void pnv_init(MachineState *machine)
char *chip_typename; char *chip_typename;
/* allocate RAM */ /* allocate RAM */
if (machine->ram_size < (1 * G_BYTE)) { if (machine->ram_size < (1 * GiB)) {
warn_report("skiboot may not work with < 1GB of RAM"); warn_report("skiboot may not work with < 1GB of RAM");
} }
@ -1174,7 +1174,7 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data)
* storage */ * storage */
mc->no_parallel = 1; mc->no_parallel = 1;
mc->default_boot_order = NULL; mc->default_boot_order = NULL;
mc->default_ram_size = 1 * G_BYTE; mc->default_ram_size = 1 * GiB;
xic->icp_get = pnv_icp_get; xic->icp_get = pnv_icp_get;
xic->ics_get = pnv_ics_get; xic->ics_get = pnv_ics_get;
xic->ics_resend = pnv_ics_resend; xic->ics_resend = pnv_ics_resend;

9
hw/ppc/ppc405_boards.c
View File

@ -22,6 +22,7 @@
* THE SOFTWARE. * THE SOFTWARE.
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "cpu.h" #include "cpu.h"
@ -40,7 +41,7 @@
#include "exec/address-spaces.h" #include "exec/address-spaces.h"
#define BIOS_FILENAME "ppc405_rom.bin" #define BIOS_FILENAME "ppc405_rom.bin"
#define BIOS_SIZE (2048 * 1024) #define BIOS_SIZE (2 * MiB)
#define KERNEL_LOAD_ADDR 0x00000000 #define KERNEL_LOAD_ADDR 0x00000000
#define INITRD_LOAD_ADDR 0x01800000 #define INITRD_LOAD_ADDR 0x01800000
@ -216,14 +217,14 @@ static void ref405ep_init(MachineState *machine)
memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0); memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0);
ram_bases[1] = 0x00000000; ram_bases[1] = 0x00000000;
ram_sizes[1] = 0x00000000; ram_sizes[1] = 0x00000000;
ram_size = 128 * 1024 * 1024; ram_size = 128 * MiB;
#ifdef DEBUG_BOARD_INIT #ifdef DEBUG_BOARD_INIT
printf("%s: register cpu\n", __func__); printf("%s: register cpu\n", __func__);
#endif #endif
env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
33333333, &pic, kernel_filename == NULL ? 0 : 1); 33333333, &pic, kernel_filename == NULL ? 0 : 1);
/* allocate SRAM */ /* allocate SRAM */
sram_size = 512 * 1024; sram_size = 512 * KiB;
memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size, memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size,
&error_fatal); &error_fatal);
memory_region_add_subregion(sysmem, 0xFFF00000, sram); memory_region_add_subregion(sysmem, 0xFFF00000, sram);
@ -589,7 +590,7 @@ static void taihu_405ep_init(MachineState *machine)
bios_size = blk_getlength(blk); bios_size = blk_getlength(blk);
/* XXX: should check that size is 32MB */ /* XXX: should check that size is 32MB */
bios_size = 32 * 1024 * 1024; bios_size = 32 * MiB;
fl_sectors = (bios_size + 65535) >> 16; fl_sectors = (bios_size + 65535) >> 16;
#ifdef DEBUG_BOARD_INIT #ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size %lx" printf("Register parallel flash %d size %lx"

7
hw/ppc/ppc405_uc.c
View File

@ -22,6 +22,7 @@
* THE SOFTWARE. * THE SOFTWARE.
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "cpu.h" #include "cpu.h"
@ -983,10 +984,10 @@ static void ppc405_ocm_init(CPUPPCState *env)
ocm = g_malloc0(sizeof(ppc405_ocm_t)); ocm = g_malloc0(sizeof(ppc405_ocm_t));
/* XXX: Size is 4096 or 0x04000000 */ /* XXX: Size is 4096 or 0x04000000 */
memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4096, memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4 * KiB,
&error_fatal); &error_fatal);
memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc", &ocm->isarc_ram, memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc",
0, 4096); &ocm->isarc_ram, 0, 4 * KiB);
qemu_register_reset(&ocm_reset, ocm); qemu_register_reset(&ocm_reset, ocm);
ppc_dcr_register(env, OCM0_ISARC, ppc_dcr_register(env, OCM0_ISARC,
ocm, &dcr_read_ocm, &dcr_write_ocm); ocm, &dcr_read_ocm, &dcr_write_ocm);

5
hw/ppc/ppc440_bamboo.c
View File

@ -12,6 +12,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
@ -49,7 +50,7 @@
#define PPC440EP_SDRAM_NR_BANKS 4 #define PPC440EP_SDRAM_NR_BANKS 4
static const unsigned int ppc440ep_sdram_bank_sizes[] = { static const unsigned int ppc440ep_sdram_bank_sizes[] = {
256<<20, 128<<20, 64<<20, 32<<20, 16<<20, 8<<20, 0 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0
}; };
static hwaddr entry; static hwaddr entry;
@ -151,7 +152,7 @@ static void main_cpu_reset(void *opaque)
CPUPPCState *env = &cpu->env; CPUPPCState *env = &cpu->env;
cpu_reset(CPU(cpu)); cpu_reset(CPU(cpu));
env->gpr[1] = (16<<20) - 8; env->gpr[1] = (16 * MiB) - 8;
env->gpr[3] = FDT_ADDR; env->gpr[3] = FDT_ADDR;
env->nip = entry; env->nip = entry;

28
hw/ppc/ppc440_uc.c
View File

@ -9,8 +9,8 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "qemu/cutils.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "cpu.h" #include "cpu.h"
@ -215,13 +215,13 @@ void ppc4xx_l2sram_init(CPUPPCState *env)
l2sram = g_malloc0(sizeof(*l2sram)); l2sram = g_malloc0(sizeof(*l2sram));
/* XXX: Size is 4*64kB for 460ex, cf. U-Boot, ppc4xx-isram.h */ /* XXX: Size is 4*64kB for 460ex, cf. U-Boot, ppc4xx-isram.h */
memory_region_init_ram(&l2sram->bank[0], NULL, "ppc4xx.l2sram_bank0", memory_region_init_ram(&l2sram->bank[0], NULL, "ppc4xx.l2sram_bank0",
64 * K_BYTE, &error_abort); 64 * KiB, &error_abort);
memory_region_init_ram(&l2sram->bank[1], NULL, "ppc4xx.l2sram_bank1", memory_region_init_ram(&l2sram->bank[1], NULL, "ppc4xx.l2sram_bank1",
64 * K_BYTE, &error_abort); 64 * KiB, &error_abort);
memory_region_init_ram(&l2sram->bank[2], NULL, "ppc4xx.l2sram_bank2", memory_region_init_ram(&l2sram->bank[2], NULL, "ppc4xx.l2sram_bank2",
64 * K_BYTE, &error_abort); 64 * KiB, &error_abort);
memory_region_init_ram(&l2sram->bank[3], NULL, "ppc4xx.l2sram_bank3", memory_region_init_ram(&l2sram->bank[3], NULL, "ppc4xx.l2sram_bank3",
64 * K_BYTE, &error_abort); 64 * KiB, &error_abort);
qemu_register_reset(&l2sram_reset, l2sram); qemu_register_reset(&l2sram_reset, l2sram);
ppc_dcr_register(env, DCR_L2CACHE_CFG, ppc_dcr_register(env, DCR_L2CACHE_CFG,
l2sram, &dcr_read_l2sram, &dcr_write_l2sram); l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
@ -513,28 +513,28 @@ static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size)
uint32_t bcr; uint32_t bcr;
switch (ram_size) { switch (ram_size) {
case (8 * M_BYTE): case (8 * MiB):
bcr = 0xffc0; bcr = 0xffc0;
break; break;
case (16 * M_BYTE): case (16 * MiB):
bcr = 0xff80; bcr = 0xff80;
break; break;
case (32 * M_BYTE): case (32 * MiB):
bcr = 0xff00; bcr = 0xff00;
break; break;
case (64 * M_BYTE): case (64 * MiB):
bcr = 0xfe00; bcr = 0xfe00;
break; break;
case (128 * M_BYTE): case (128 * MiB):
bcr = 0xfc00; bcr = 0xfc00;
break; break;
case (256 * M_BYTE): case (256 * MiB):
bcr = 0xf800; bcr = 0xf800;
break; break;
case (512 * M_BYTE): case (512 * MiB):
bcr = 0xf000; bcr = 0xf000;
break; break;
case (1 * G_BYTE): case (1 * GiB):
bcr = 0xe000; bcr = 0xe000;
break; break;
default: default:
@ -561,7 +561,7 @@ static target_ulong sdram_size(uint32_t bcr)
if (sh == 0) { if (sh == 0) {
size = -1; size = -1;
} else { } else {
size = 8 * M_BYTE * sh; size = 8 * MiB * sh;
} }
return size; return size;

22
hw/ppc/ppc4xx_devs.c
View File

@ -22,6 +22,7 @@
* THE SOFTWARE. * THE SOFTWARE.
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "cpu.h" #include "cpu.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "hw/ppc/ppc.h" #include "hw/ppc/ppc.h"
@ -29,6 +30,7 @@
#include "hw/boards.h" #include "hw/boards.h"
#include "qemu/log.h" #include "qemu/log.h"
#include "exec/address-spaces.h" #include "exec/address-spaces.h"
#include "qemu/error-report.h"
#define DEBUG_UIC #define DEBUG_UIC
@ -353,25 +355,25 @@ static uint32_t sdram_bcr (hwaddr ram_base,
uint32_t bcr; uint32_t bcr;
switch (ram_size) { switch (ram_size) {
case (4 * 1024 * 1024): case 4 * MiB:
bcr = 0x00000000; bcr = 0x00000000;
break; break;
case (8 * 1024 * 1024): case 8 * MiB:
bcr = 0x00020000; bcr = 0x00020000;
break; break;
case (16 * 1024 * 1024): case 16 * MiB:
bcr = 0x00040000; bcr = 0x00040000;
break; break;
case (32 * 1024 * 1024): case 32 * MiB:
bcr = 0x00060000; bcr = 0x00060000;
break; break;
case (64 * 1024 * 1024): case 64 * MiB:
bcr = 0x00080000; bcr = 0x00080000;
break; break;
case (128 * 1024 * 1024): case 128 * MiB:
bcr = 0x000A0000; bcr = 0x000A0000;
break; break;
case (256 * 1024 * 1024): case 256 * MiB:
bcr = 0x000C0000; bcr = 0x000C0000;
break; break;
default: default:
@ -399,7 +401,7 @@ static target_ulong sdram_size (uint32_t bcr)
if (sh == 7) if (sh == 7)
size = -1; size = -1;
else else
size = (4 * 1024 * 1024) << sh; size = (4 * MiB) << sh;
return size; return size;
} }
@ -702,8 +704,8 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
ram_size -= size_left; ram_size -= size_left;
if (size_left) { if (size_left) {
printf("Truncating memory to %d MiB to fit SDRAM controller limits.\n", error_report("Truncating memory to %" PRId64 " MiB to fit SDRAM"
(int)(ram_size >> 20)); " controller limits", ram_size / MiB);
} }
memory_region_allocate_system_memory(ram, NULL, "ppc4xx.sdram", ram_size); memory_region_allocate_system_memory(ram, NULL, "ppc4xx.sdram", ram_size);

3
hw/ppc/ppce500_spin.c
View File

@ -28,6 +28,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "hw/sysbus.h" #include "hw/sysbus.h"
#include "sysemu/hw_accel.h" #include "sysemu/hw_accel.h"
@ -89,7 +90,7 @@ static void spin_kick(CPUState *cs, run_on_cpu_data data)
PowerPCCPU *cpu = POWERPC_CPU(cs); PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env; CPUPPCState *env = &cpu->env;
SpinInfo *curspin = data.host_ptr; SpinInfo *curspin = data.host_ptr;
hwaddr map_size = 64 * 1024 * 1024; hwaddr map_size = 64 * MiB;
hwaddr map_start; hwaddr map_start;
cpu_synchronize_state(cs); cpu_synchronize_state(cs);

6
hw/ppc/prep.c
View File

@ -50,7 +50,7 @@
#include "exec/address-spaces.h" #include "exec/address-spaces.h"
#include "trace.h" #include "trace.h"
#include "elf.h" #include "elf.h"
#include "qemu/cutils.h" #include "qemu/units.h"
#include "kvm_ppc.h" #include "kvm_ppc.h"
/* SMP is not enabled, for now */ /* SMP is not enabled, for now */
@ -60,7 +60,7 @@
#define CFG_ADDR 0xf0000510 #define CFG_ADDR 0xf0000510
#define BIOS_SIZE (1024 * 1024) #define BIOS_SIZE (1 * MiB)
#define BIOS_FILENAME "ppc_rom.bin" #define BIOS_FILENAME "ppc_rom.bin"
#define KERNEL_LOAD_ADDR 0x01000000 #define KERNEL_LOAD_ADDR 0x01000000
#define INITRD_LOAD_ADDR 0x01800000 #define INITRD_LOAD_ADDR 0x01800000
@ -884,7 +884,7 @@ static void ibm_40p_machine_init(MachineClass *mc)
mc->desc = "IBM RS/6000 7020 (40p)", mc->desc = "IBM RS/6000 7020 (40p)",
mc->init = ibm_40p_init; mc->init = ibm_40p_init;
mc->max_cpus = 1; mc->max_cpus = 1;
mc->default_ram_size = 128 * M_BYTE; mc->default_ram_size = 128 * MiB;
mc->block_default_type = IF_SCSI; mc->block_default_type = IF_SCSI;
mc->default_boot_order = "c"; mc->default_boot_order = "c";
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604"); mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604");

13
hw/ppc/rs6000_mc.c
View File

@ -18,6 +18,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/isa/isa.h" #include "hw/isa/isa.h"
#include "exec/address-spaces.h" #include "exec/address-spaces.h"
#include "hw/boards.h" #include "hw/boards.h"
@ -109,7 +110,7 @@ static void rs6000mc_port0820_write(void *opaque, uint32_t addr, uint32_t val)
size = end_address - start_address; size = end_address - start_address;
memory_region_set_enabled(&s->simm[socket - 1], size != 0); memory_region_set_enabled(&s->simm[socket - 1], size != 0);
memory_region_set_address(&s->simm[socket - 1], memory_region_set_address(&s->simm[socket - 1],
start_address * 8 * 1024 * 1024); start_address * 8 * MiB);
} }
} }
} }
@ -140,7 +141,7 @@ static void rs6000mc_realize(DeviceState *dev, Error **errp)
{ {
RS6000MCState *s = RS6000MC_DEVICE(dev); RS6000MCState *s = RS6000MC_DEVICE(dev);
int socket = 0; int socket = 0;
unsigned int ram_size = s->ram_size / (1024 * 1024); unsigned int ram_size = s->ram_size / MiB;
while (socket < 6) { while (socket < 6) {
if (ram_size >= 64) { if (ram_size >= 64) {
@ -163,8 +164,8 @@ static void rs6000mc_realize(DeviceState *dev, Error **errp)
char name[] = "simm.?"; char name[] = "simm.?";
name[5] = socket + '0'; name[5] = socket + '0';
memory_region_allocate_system_memory(&s->simm[socket], OBJECT(dev), memory_region_allocate_system_memory(&s->simm[socket], OBJECT(dev),
name, s->simm_size[socket] name,
* 1024 * 1024); s->simm_size[socket] * MiB);
memory_region_add_subregion_overlap(get_system_memory(), 0, memory_region_add_subregion_overlap(get_system_memory(), 0,
&s->simm[socket], socket); &s->simm[socket], socket);
} }
@ -172,8 +173,8 @@ static void rs6000mc_realize(DeviceState *dev, Error **errp)
if (ram_size) { if (ram_size) {
/* unable to push all requested RAM in SIMMs */ /* unable to push all requested RAM in SIMMs */
error_setg(errp, "RAM size incompatible with this board. " error_setg(errp, "RAM size incompatible with this board. "
"Try again with something else, like %d MB", "Try again with something else, like %" PRId64 " MB",
s->ram_size / 1024 / 1024 - ram_size); s->ram_size / MiB - ram_size);
return; return;
} }

18
hw/ppc/sam460ex.c
View File

@ -12,8 +12,8 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "qemu/cutils.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "hw/hw.h" #include "hw/hw.h"
@ -46,7 +46,7 @@
/* from Sam460 U-Boot include/configs/Sam460ex.h */ /* from Sam460 U-Boot include/configs/Sam460ex.h */
#define FLASH_BASE 0xfff00000 #define FLASH_BASE 0xfff00000
#define FLASH_BASE_H 0x4 #define FLASH_BASE_H 0x4
#define FLASH_SIZE (1 << 20) #define FLASH_SIZE (1 * MiB)
#define UBOOT_LOAD_BASE 0xfff80000 #define UBOOT_LOAD_BASE 0xfff80000
#define UBOOT_SIZE 0x00080000 #define UBOOT_SIZE 0x00080000
#define UBOOT_ENTRY 0xfffffffc #define UBOOT_ENTRY 0xfffffffc
@ -71,7 +71,7 @@
/* FIXME: See u-boot.git 8ac41e, also fix in ppc440_uc.c */ /* FIXME: See u-boot.git 8ac41e, also fix in ppc440_uc.c */
static const unsigned int ppc460ex_sdram_bank_sizes[] = { static const unsigned int ppc460ex_sdram_bank_sizes[] = {
1024 << 20, 512 << 20, 256 << 20, 128 << 20, 64 << 20, 32 << 20, 0 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 0
}; };
struct boot_info { struct boot_info {
@ -126,7 +126,7 @@ static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size)
int i; int i;
/* work in terms of MB */ /* work in terms of MB */
ram_size >>= 20; ram_size /= MiB;
while ((ram_size >= 4) && (nbanks <= 2)) { while ((ram_size >= 4) && (nbanks <= 2)) {
int sz_log2 = MIN(31 - clz32(ram_size), 14); int sz_log2 = MIN(31 - clz32(ram_size), 14);
@ -225,7 +225,7 @@ static int sam460ex_load_uboot(void)
fl_sectors = (bios_size + 65535) >> 16; fl_sectors = (bios_size + 65535) >> 16;
if (!pflash_cfi01_register(base, NULL, "sam460ex.flash", bios_size, if (!pflash_cfi01_register(base, NULL, "sam460ex.flash", bios_size,
blk, (64 * 1024), fl_sectors, blk, 64 * KiB, fl_sectors,
1, 0x89, 0x18, 0x0000, 0x0, 1)) { 1, 0x89, 0x18, 0x0000, 0x0, 1)) {
error_report("qemu: Error registering flash memory."); error_report("qemu: Error registering flash memory.");
/* XXX: return an error instead? */ /* XXX: return an error instead? */
@ -359,14 +359,14 @@ static void main_cpu_reset(void *opaque)
/* either we have a kernel to boot or we jump to U-Boot */ /* either we have a kernel to boot or we jump to U-Boot */
if (bi->entry != UBOOT_ENTRY) { if (bi->entry != UBOOT_ENTRY) {
env->gpr[1] = (16 << 20) - 8; env->gpr[1] = (16 * MiB) - 8;
env->gpr[3] = FDT_ADDR; env->gpr[3] = FDT_ADDR;
env->nip = bi->entry; env->nip = bi->entry;
/* Create a mapping for the kernel. */ /* Create a mapping for the kernel. */
mmubooke_create_initial_mapping(env, 0, 0); mmubooke_create_initial_mapping(env, 0, 0);
env->gpr[6] = tswap32(EPAPR_MAGIC); env->gpr[6] = tswap32(EPAPR_MAGIC);
env->gpr[7] = (16 << 20) - 8; /*bi->ima_size;*/ env->gpr[7] = (16 * MiB) - 8; /* bi->ima_size; */
} else { } else {
env->nip = UBOOT_ENTRY; env->nip = UBOOT_ENTRY;
@ -479,7 +479,7 @@ static void sam460ex_init(MachineState *machine)
/* 256K of L2 cache as memory */ /* 256K of L2 cache as memory */
ppc4xx_l2sram_init(env); ppc4xx_l2sram_init(env);
/* FIXME: remove this after fixing l2sram mapping in ppc440_uc.c? */ /* FIXME: remove this after fixing l2sram mapping in ppc440_uc.c? */
memory_region_init_ram(l2cache_ram, NULL, "ppc440.l2cache_ram", 256 << 10, memory_region_init_ram(l2cache_ram, NULL, "ppc440.l2cache_ram", 256 * KiB,
&error_abort); &error_abort);
memory_region_add_subregion(address_space_mem, 0x400000000LL, l2cache_ram); memory_region_add_subregion(address_space_mem, 0x400000000LL, l2cache_ram);
@ -597,7 +597,7 @@ static void sam460ex_machine_init(MachineClass *mc)
mc->desc = "aCube Sam460ex"; mc->desc = "aCube Sam460ex";
mc->init = sam460ex_init; mc->init = sam460ex_init;
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb"); mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb");
mc->default_ram_size = 512 * M_BYTE; mc->default_ram_size = 512 * MiB;
} }
DEFINE_MACHINE("sam460ex", sam460ex_machine_init) DEFINE_MACHINE("sam460ex", sam460ex_machine_init)

18
hw/ppc/spapr.c
View File

@ -2322,17 +2322,17 @@ static void spapr_validate_node_memory(MachineState *machine, Error **errp)
if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
error_setg(errp, "Memory size 0x" RAM_ADDR_FMT error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
" is not aligned to %llu MiB", " is not aligned to %" PRIu64 " MiB",
machine->ram_size, machine->ram_size,
SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); SPAPR_MEMORY_BLOCK_SIZE / MiB);
return; return;
} }
if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
" is not aligned to %llu MiB", " is not aligned to %" PRIu64 " MiB",
machine->ram_size, machine->ram_size,
SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); SPAPR_MEMORY_BLOCK_SIZE / MiB);
return; return;
} }
@ -2340,9 +2340,9 @@ static void spapr_validate_node_memory(MachineState *machine, Error **errp)
if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
error_setg(errp, error_setg(errp,
"Node %d memory size 0x%" PRIx64 "Node %d memory size 0x%" PRIx64
" is not aligned to %llu MiB", " is not aligned to %" PRIu64 " MiB",
i, numa_info[i].node_mem, i, numa_info[i].node_mem,
SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); SPAPR_MEMORY_BLOCK_SIZE / MiB);
return; return;
} }
} }
@ -2763,7 +2763,7 @@ static void spapr_machine_init(MachineState *machine)
} }
} }
if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) {
error_report( error_report(
"pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
MIN_RMA_SLOF); MIN_RMA_SLOF);
@ -3209,7 +3209,7 @@ static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
if (size % SPAPR_MEMORY_BLOCK_SIZE) { if (size % SPAPR_MEMORY_BLOCK_SIZE) {
error_setg(errp, "Hotplugged memory size must be a multiple of " error_setg(errp, "Hotplugged memory size must be a multiple of "
"%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB);
return; return;
} }
@ -3961,7 +3961,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
mc->max_cpus = 1024; mc->max_cpus = 1024;
mc->no_parallel = 1; mc->no_parallel = 1;
mc->default_boot_order = ""; mc->default_boot_order = "";
mc->default_ram_size = 512 * M_BYTE; mc->default_ram_size = 512 * MiB;
mc->kvm_type = spapr_kvm_type; mc->kvm_type = spapr_kvm_type;
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE);
mc->pci_allow_0_address = true; mc->pci_allow_0_address = true;

4
hw/ppc/spapr_rtas.c
View File

@ -237,11 +237,11 @@ static void rtas_ibm_get_system_parameter(PowerPCCPU *cpu,
switch (parameter) { switch (parameter) {
case RTAS_SYSPARM_SPLPAR_CHARACTERISTICS: { case RTAS_SYSPARM_SPLPAR_CHARACTERISTICS: {
char *param_val = g_strdup_printf("MaxEntCap=%d," char *param_val = g_strdup_printf("MaxEntCap=%d,"
"DesMem=%llu," "DesMem=%" PRIu64 ","
"DesProcs=%d," "DesProcs=%d,"
"MaxPlatProcs=%d", "MaxPlatProcs=%d",
max_cpus, max_cpus,
current_machine->ram_size / M_BYTE, current_machine->ram_size / MiB,
smp_cpus, smp_cpus,
max_cpus); max_cpus);
ret = sysparm_st(buffer, length, param_val, strlen(param_val) + 1); ret = sysparm_st(buffer, length, param_val, strlen(param_val) + 1);

7
hw/ppc/virtex_ml507.c
View File

@ -23,6 +23,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "cpu.h" #include "cpu.h"
#include "hw/sysbus.h" #include "hw/sysbus.h"
#include "hw/hw.h" #include "hw/hw.h"
@ -45,7 +46,7 @@
#include "ppc405.h" #include "ppc405.h"
#define EPAPR_MAGIC (0x45504150) #define EPAPR_MAGIC (0x45504150)
#define FLASH_SIZE (16 * 1024 * 1024) #define FLASH_SIZE (16 * MiB)
#define INTC_BASEADDR 0x81800000 #define INTC_BASEADDR 0x81800000
#define UART16550_BASEADDR 0x83e01003 #define UART16550_BASEADDR 0x83e01003
@ -127,7 +128,7 @@ static void main_cpu_reset(void *opaque)
* r8: 0 * r8: 0
* r9: 0 * r9: 0
*/ */
env->gpr[1] = (16<<20) - 8; env->gpr[1] = (16 * MiB) - 8;
/* Provide a device-tree. */ /* Provide a device-tree. */
env->gpr[3] = bi->fdt; env->gpr[3] = bi->fdt;
env->nip = bi->bootstrap_pc; env->nip = bi->bootstrap_pc;
@ -235,7 +236,7 @@ static void virtex_init(MachineState *machine)
dinfo = drive_get(IF_PFLASH, 0, 0); dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi01_register(PFLASH_BASEADDR, NULL, "virtex.flash", FLASH_SIZE, pflash_cfi01_register(PFLASH_BASEADDR, NULL, "virtex.flash", FLASH_SIZE,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
(64 * 1024), FLASH_SIZE >> 16, 64 * KiB, FLASH_SIZE >> 16,
1, 0x89, 0x18, 0x0000, 0x0, 1); 1, 0x89, 0x18, 0x0000, 0x0, 1);
cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT]; cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];

3
hw/rdma/vmw/pvrdma.h
View File

@ -16,6 +16,7 @@
#ifndef PVRDMA_PVRDMA_H #ifndef PVRDMA_PVRDMA_H
#define PVRDMA_PVRDMA_H #define PVRDMA_PVRDMA_H
#include "qemu/units.h"
#include "hw/pci/pci.h" #include "hw/pci/pci.h"
#include "hw/pci/msix.h" #include "hw/pci/msix.h"
@ -30,7 +31,7 @@
#define RDMA_MSIX_BAR_IDX 0 #define RDMA_MSIX_BAR_IDX 0
#define RDMA_REG_BAR_IDX 1 #define RDMA_REG_BAR_IDX 1
#define RDMA_UAR_BAR_IDX 2 #define RDMA_UAR_BAR_IDX 2
#define RDMA_BAR0_MSIX_SIZE (16 * 1024) #define RDMA_BAR0_MSIX_SIZE (16 * KiB)
#define RDMA_BAR1_REGS_SIZE 64 #define RDMA_BAR1_REGS_SIZE 64
#define RDMA_BAR2_UAR_SIZE (0x1000 * MAX_UCS) /* each uc gets page */ #define RDMA_BAR2_UAR_SIZE (0x1000 * MAX_UCS) /* each uc gets page */

3
hw/riscv/virt.c
View File

@ -19,6 +19,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/log.h" #include "qemu/log.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
#include "qapi/error.h" #include "qapi/error.h"
@ -84,7 +85,7 @@ static hwaddr load_initrd(const char *filename, uint64_t mem_size,
* halfway into RAM, and for boards with 256MB of RAM or more we put * halfway into RAM, and for boards with 256MB of RAM or more we put
* the initrd at 128MB. * the initrd at 128MB.
*/ */
*start = kernel_entry + MIN(mem_size / 2, 128 * 1024 * 1024); *start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
size = load_ramdisk(filename, *start, mem_size - *start); size = load_ramdisk(filename, *start, mem_size - *start);
if (size == -1) { if (size == -1) {

3
hw/s390x/s390-skeys.c
View File

@ -10,6 +10,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/boards.h" #include "hw/boards.h"
#include "hw/s390x/storage-keys.h" #include "hw/s390x/storage-keys.h"
#include "qapi/error.h" #include "qapi/error.h"
@ -19,7 +20,7 @@
#include "sysemu/kvm.h" #include "sysemu/kvm.h"
#include "migration/register.h" #include "migration/register.h"
#define S390_SKEYS_BUFFER_SIZE 131072 /* Room for 128k storage keys */ #define S390_SKEYS_BUFFER_SIZE (128 * KiB) /* Room for 128k storage keys */
#define S390_SKEYS_SAVE_FLAG_EOS 0x01 #define S390_SKEYS_SAVE_FLAG_EOS 0x01
#define S390_SKEYS_SAVE_FLAG_SKEYS 0x02 #define S390_SKEYS_SAVE_FLAG_SKEYS 0x02
#define S390_SKEYS_SAVE_FLAG_ERROR 0x04 #define S390_SKEYS_SAVE_FLAG_ERROR 0x04

3
hw/s390x/s390-stattrib.c
View File

@ -10,6 +10,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/boards.h" #include "hw/boards.h"
#include "cpu.h" #include "cpu.h"
#include "migration/qemu-file.h" #include "migration/qemu-file.h"
@ -20,7 +21,7 @@
#include "qapi/error.h" #include "qapi/error.h"
#include "qapi/qmp/qdict.h" #include "qapi/qmp/qdict.h"
#define CMMA_BLOCK_SIZE (1 << 10) #define CMMA_BLOCK_SIZE (1 * KiB)
#define STATTR_FLAG_EOS 0x01ULL #define STATTR_FLAG_EOS 0x01ULL
#define STATTR_FLAG_MORE 0x02ULL #define STATTR_FLAG_MORE 0x02ULL

3
hw/s390x/sclp.c
View File

@ -13,6 +13,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "cpu.h" #include "cpu.h"
#include "sysemu/sysemu.h" #include "sysemu/sysemu.h"
@ -289,7 +290,7 @@ static void sclp_realize(DeviceState *dev, Error **errp)
ret = s390_set_memory_limit(machine->maxram_size, &hw_limit); ret = s390_set_memory_limit(machine->maxram_size, &hw_limit);
if (ret == -E2BIG) { if (ret == -E2BIG) {
error_setg(&err, "host supports a maximum of %" PRIu64 " GB", error_setg(&err, "host supports a maximum of %" PRIu64 " GB",
hw_limit >> 30); hw_limit / GiB);
} else if (ret) { } else if (ret) {
error_setg(&err, "setting the guest size failed"); error_setg(&err, "setting the guest size failed");
} }

9
hw/scsi/scsi-disk.c
View File

@ -29,6 +29,7 @@ do { printf("scsi-disk: " fmt , ## __VA_ARGS__); } while (0)
#endif #endif
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
#include "hw/scsi/scsi.h" #include "hw/scsi/scsi.h"
@ -44,13 +45,13 @@ do { printf("scsi-disk: " fmt , ## __VA_ARGS__); } while (0)
#include <scsi/sg.h> #include <scsi/sg.h>
#endif #endif
#define SCSI_WRITE_SAME_MAX 524288 #define SCSI_WRITE_SAME_MAX (512 * KiB)
#define SCSI_DMA_BUF_SIZE 131072 #define SCSI_DMA_BUF_SIZE (128 * KiB)
#define SCSI_MAX_INQUIRY_LEN 256 #define SCSI_MAX_INQUIRY_LEN 256
#define SCSI_MAX_MODE_LEN 256 #define SCSI_MAX_MODE_LEN 256
#define DEFAULT_DISCARD_GRANULARITY 4096 #define DEFAULT_DISCARD_GRANULARITY (4 * KiB)
#define DEFAULT_MAX_UNMAP_SIZE (1 << 30) /* 1 GB */ #define DEFAULT_MAX_UNMAP_SIZE (1 * GiB)
#define DEFAULT_MAX_IO_SIZE INT_MAX /* 2 GB - 1 block */ #define DEFAULT_MAX_IO_SIZE INT_MAX /* 2 GB - 1 block */
#define TYPE_SCSI_DISK_BASE "scsi-disk-base" #define TYPE_SCSI_DISK_BASE "scsi-disk-base"

8
hw/sd/sd.c
View File

@ -31,6 +31,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/qdev.h" #include "hw/qdev.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "hw/registerfields.h" #include "hw/registerfields.h"
@ -38,7 +39,6 @@
#include "hw/sd/sd.h" #include "hw/sd/sd.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu/bitmap.h" #include "qemu/bitmap.h"
#include "qemu/cutils.h"
#include "hw/qdev-properties.h" #include "hw/qdev-properties.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
#include "qemu/timer.h" #include "qemu/timer.h"
@ -305,7 +305,7 @@ static void sd_ocr_powerup(void *opaque)
/* card power-up OK */ /* card power-up OK */
sd->ocr = FIELD_DP32(sd->ocr, OCR, CARD_POWER_UP, 1); sd->ocr = FIELD_DP32(sd->ocr, OCR, CARD_POWER_UP, 1);
if (sd->size > 1 * G_BYTE) { if (sd->size > 1 * GiB) {
sd->ocr = FIELD_DP32(sd->ocr, OCR, CARD_CAPACITY, 1); sd->ocr = FIELD_DP32(sd->ocr, OCR, CARD_CAPACITY, 1);
} }
} }
@ -377,7 +377,7 @@ static void sd_set_csd(SDState *sd, uint64_t size)
uint32_t sectsize = (1 << (SECTOR_SHIFT + 1)) - 1; uint32_t sectsize = (1 << (SECTOR_SHIFT + 1)) - 1;
uint32_t wpsize = (1 << (WPGROUP_SHIFT + 1)) - 1; uint32_t wpsize = (1 << (WPGROUP_SHIFT + 1)) - 1;
if (size <= 1 * G_BYTE) { /* Standard Capacity SD */ if (size <= 1 * GiB) { /* Standard Capacity SD */
sd->csd[0] = 0x00; /* CSD structure */ sd->csd[0] = 0x00; /* CSD structure */
sd->csd[1] = 0x26; /* Data read access-time-1 */ sd->csd[1] = 0x26; /* Data read access-time-1 */
sd->csd[2] = 0x00; /* Data read access-time-2 */ sd->csd[2] = 0x00; /* Data read access-time-2 */
@ -403,7 +403,7 @@ static void sd_set_csd(SDState *sd, uint64_t size)
((HWBLOCK_SHIFT << 6) & 0xc0); ((HWBLOCK_SHIFT << 6) & 0xc0);
sd->csd[14] = 0x00; /* File format group */ sd->csd[14] = 0x00; /* File format group */
} else { /* SDHC */ } else { /* SDHC */
size /= 512 * 1024; size /= 512 * KiB;
size -= 1; size -= 1;
sd->csd[0] = 0x40; sd->csd[0] = 0x40;
sd->csd[1] = 0x0e; sd->csd[1] = 0x0e;

8
hw/sd/sdhci.c
View File

@ -23,6 +23,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "hw/hw.h" #include "hw/hw.h"
@ -32,7 +33,6 @@
#include "hw/sd/sdhci.h" #include "hw/sd/sdhci.h"
#include "sdhci-internal.h" #include "sdhci-internal.h"
#include "qemu/log.h" #include "qemu/log.h"
#include "qemu/cutils.h"
#include "trace.h" #include "trace.h"
#define TYPE_SDHCI_BUS "sdhci-bus" #define TYPE_SDHCI_BUS "sdhci-bus"
@ -409,7 +409,7 @@ static void sdhci_end_transfer(SDHCIState *s)
/* /*
* Programmed i/o data transfer * Programmed i/o data transfer
*/ */
#define BLOCK_SIZE_MASK (4 * K_BYTE - 1) #define BLOCK_SIZE_MASK (4 * KiB - 1)
/* Fill host controller's read buffer with BLKSIZE bytes of data from card */ /* Fill host controller's read buffer with BLKSIZE bytes of data from card */
static void sdhci_read_block_from_card(SDHCIState *s) static void sdhci_read_block_from_card(SDHCIState *s)
@ -737,7 +737,7 @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr)
if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) { if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) {
dscr->length = (uint16_t)extract32(adma1, 12, 16); dscr->length = (uint16_t)extract32(adma1, 12, 16);
} else { } else {
dscr->length = 4096; dscr->length = 4 * KiB;
} }
break; break;
case SDHC_CTRL_ADMA2_64: case SDHC_CTRL_ADMA2_64:
@ -785,7 +785,7 @@ static void sdhci_do_adma(SDHCIState *s)
return; return;
} }
length = dscr.length ? dscr.length : 65536; length = dscr.length ? dscr.length : 64 * KiB;
switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) { switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) {
case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */ case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */

3
hw/sh4/r2d.c
View File

@ -24,6 +24,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "cpu.h" #include "cpu.h"
@ -291,7 +292,7 @@ static void r2d_init(MachineState *machine)
dinfo = drive_get(IF_PFLASH, 0, 0); dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi02_register(0x0, NULL, "r2d.flash", FLASH_SIZE, pflash_cfi02_register(0x0, NULL, "r2d.flash", FLASH_SIZE,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
(16 * 1024), FLASH_SIZE >> 16, 16 * KiB, FLASH_SIZE >> 16,
1, 4, 0x0000, 0x0000, 0x0000, 0x0000, 1, 4, 0x0000, 0x0000, 0x0000, 0x0000,
0x555, 0x2aa, 0); 0x555, 0x2aa, 0);

15
hw/smbios/smbios.c
View File

@ -16,6 +16,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu/config-file.h" #include "qemu/config-file.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
@ -625,10 +626,6 @@ static void smbios_build_type_11_table(void)
SMBIOS_BUILD_TABLE_POST; SMBIOS_BUILD_TABLE_POST;
} }
#define ONE_KB ((ram_addr_t)1 << 10)
#define ONE_MB ((ram_addr_t)1 << 20)
#define ONE_GB ((ram_addr_t)1 << 30)
#define MAX_T16_STD_SZ 0x80000000 /* 2T in Kilobytes */ #define MAX_T16_STD_SZ 0x80000000 /* 2T in Kilobytes */
static void smbios_build_type_16_table(unsigned dimm_cnt) static void smbios_build_type_16_table(unsigned dimm_cnt)
@ -640,7 +637,7 @@ static void smbios_build_type_16_table(unsigned dimm_cnt)
t->location = 0x01; /* Other */ t->location = 0x01; /* Other */
t->use = 0x03; /* System memory */ t->use = 0x03; /* System memory */
t->error_correction = 0x06; /* Multi-bit ECC (for Microsoft, per SeaBIOS) */ t->error_correction = 0x06; /* Multi-bit ECC (for Microsoft, per SeaBIOS) */
size_kb = QEMU_ALIGN_UP(ram_size, ONE_KB) / ONE_KB; size_kb = QEMU_ALIGN_UP(ram_size, KiB) / KiB;
if (size_kb < MAX_T16_STD_SZ) { if (size_kb < MAX_T16_STD_SZ) {
t->maximum_capacity = cpu_to_le32(size_kb); t->maximum_capacity = cpu_to_le32(size_kb);
t->extended_maximum_capacity = cpu_to_le64(0); t->extended_maximum_capacity = cpu_to_le64(0);
@ -668,7 +665,7 @@ static void smbios_build_type_17_table(unsigned instance, uint64_t size)
t->memory_error_information_handle = cpu_to_le16(0xFFFE); /* Not provided */ t->memory_error_information_handle = cpu_to_le16(0xFFFE); /* Not provided */
t->total_width = cpu_to_le16(0xFFFF); /* Unknown */ t->total_width = cpu_to_le16(0xFFFF); /* Unknown */
t->data_width = cpu_to_le16(0xFFFF); /* Unknown */ t->data_width = cpu_to_le16(0xFFFF); /* Unknown */
size_mb = QEMU_ALIGN_UP(size, ONE_MB) / ONE_MB; size_mb = QEMU_ALIGN_UP(size, MiB) / MiB;
if (size_mb < MAX_T17_STD_SZ) { if (size_mb < MAX_T17_STD_SZ) {
t->size = cpu_to_le16(size_mb); t->size = cpu_to_le16(size_mb);
t->extended_size = cpu_to_le32(0); t->extended_size = cpu_to_le32(0);
@ -707,8 +704,8 @@ static void smbios_build_type_19_table(unsigned instance,
end = start + size - 1; end = start + size - 1;
assert(end > start); assert(end > start);
start_kb = start / ONE_KB; start_kb = start / KiB;
end_kb = end / ONE_KB; end_kb = end / KiB;
if (start_kb < UINT32_MAX && end_kb < UINT32_MAX) { if (start_kb < UINT32_MAX && end_kb < UINT32_MAX) {
t->starting_address = cpu_to_le32(start_kb); t->starting_address = cpu_to_le32(start_kb);
t->ending_address = cpu_to_le32(end_kb); t->ending_address = cpu_to_le32(end_kb);
@ -869,7 +866,7 @@ void smbios_get_tables(const struct smbios_phys_mem_area *mem_array,
smbios_build_type_11_table(); smbios_build_type_11_table();
#define MAX_DIMM_SZ (16ll * ONE_GB) #define MAX_DIMM_SZ (16 * GiB)
#define GET_DIMM_SZ ((i < dimm_cnt - 1) ? MAX_DIMM_SZ \ #define GET_DIMM_SZ ((i < dimm_cnt - 1) ? MAX_DIMM_SZ \
: ((ram_size - 1) % MAX_DIMM_SZ) + 1) : ((ram_size - 1) % MAX_DIMM_SZ) + 1)

10
hw/sparc/leon3.c
View File

@ -22,6 +22,7 @@
* THE SOFTWARE. * THE SOFTWARE.
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu-common.h" #include "qemu-common.h"
@ -139,9 +140,10 @@ static void leon3_generic_hw_init(MachineState *machine)
env->qemu_irq_ack = leon3_irq_manager; env->qemu_irq_ack = leon3_irq_manager;
/* Allocate RAM */ /* Allocate RAM */
if ((uint64_t)ram_size > (1UL << 30)) { if (ram_size > 1 * GiB) {
error_report("Too much memory for this machine: %d, maximum 1G", error_report("Too much memory for this machine: %" PRId64 "MB,"
(unsigned int)(ram_size / (1024 * 1024))); " maximum 1G",
ram_size / MiB);
exit(1); exit(1);
} }
@ -149,7 +151,7 @@ static void leon3_generic_hw_init(MachineState *machine)
memory_region_add_subregion(address_space_mem, 0x40000000, ram); memory_region_add_subregion(address_space_mem, 0x40000000, ram);
/* Allocate BIOS */ /* Allocate BIOS */
prom_size = 8 * 1024 * 1024; /* 8Mb */ prom_size = 8 * MiB;
memory_region_init_ram(prom, NULL, "Leon3.bios", prom_size, &error_fatal); memory_region_init_ram(prom, NULL, "Leon3.bios", prom_size, &error_fatal);
memory_region_set_readonly(prom, true); memory_region_set_readonly(prom, true);
memory_region_add_subregion(address_space_mem, 0x00000000, prom); memory_region_add_subregion(address_space_mem, 0x00000000, prom);

10
hw/sparc/sun4m.c
View File

@ -22,6 +22,7 @@
* THE SOFTWARE. * THE SOFTWARE.
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "cpu.h" #include "cpu.h"
@ -45,7 +46,6 @@
#include "hw/loader.h" #include "hw/loader.h"
#include "elf.h" #include "elf.h"
#include "trace.h" #include "trace.h"
#include "qemu/cutils.h"
/* /*
* Sun4m architecture was used in the following machines: * Sun4m architecture was used in the following machines:
@ -66,7 +66,7 @@
#define KERNEL_LOAD_ADDR 0x00004000 #define KERNEL_LOAD_ADDR 0x00004000
#define CMDLINE_ADDR 0x007ff000 #define CMDLINE_ADDR 0x007ff000
#define INITRD_LOAD_ADDR 0x00800000 #define INITRD_LOAD_ADDR 0x00800000
#define PROM_SIZE_MAX (1024 * 1024) #define PROM_SIZE_MAX (1 * MiB)
#define PROM_VADDR 0xffd00000 #define PROM_VADDR 0xffd00000
#define PROM_FILENAME "openbios-sparc32" #define PROM_FILENAME "openbios-sparc32"
#define CFG_ADDR 0xd00000510ULL #define CFG_ADDR 0xd00000510ULL
@ -774,9 +774,9 @@ static void ram_init(hwaddr addr, ram_addr_t RAM_size,
/* allocate RAM */ /* allocate RAM */
if ((uint64_t)RAM_size > max_mem) { if ((uint64_t)RAM_size > max_mem) {
error_report("Too much memory for this machine: %d, maximum %d", error_report("Too much memory for this machine: %" PRId64 ","
(unsigned int)(RAM_size / (1024 * 1024)), " maximum %" PRId64,
(unsigned int)(max_mem / (1024 * 1024))); RAM_size / MiB, max_mem / MiB);
exit(1); exit(1);
} }
dev = qdev_create(NULL, "memory"); dev = qdev_create(NULL, "memory");

3
hw/sparc64/niagara.c
View File

@ -23,6 +23,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "cpu.h" #include "cpu.h"
#include "hw/hw.h" #include "hw/hw.h"
@ -84,7 +85,7 @@ typedef struct NiagaraBoardState {
#define NIAGARA_PROM_BASE 0xfff0000000ULL #define NIAGARA_PROM_BASE 0xfff0000000ULL
#define NIAGARA_Q_OFFSET 0x10000ULL #define NIAGARA_Q_OFFSET 0x10000ULL
#define NIAGARA_OBP_OFFSET 0x80000ULL #define NIAGARA_OBP_OFFSET 0x80000ULL
#define PROM_SIZE_MAX (4 * 1024 * 1024) #define PROM_SIZE_MAX (4 * MiB)
static void add_rom_or_fail(const char *file, const hwaddr addr) static void add_rom_or_fail(const char *file, const hwaddr addr)
{ {

4
hw/sparc64/sun4u.c
View File

@ -22,6 +22,7 @@
* THE SOFTWARE. * THE SOFTWARE.
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu-common.h" #include "qemu-common.h"
@ -52,11 +53,10 @@
#include "hw/loader.h" #include "hw/loader.h"
#include "elf.h" #include "elf.h"
#include "trace.h" #include "trace.h"
#include "qemu/cutils.h"
#define KERNEL_LOAD_ADDR 0x00404000 #define KERNEL_LOAD_ADDR 0x00404000
#define CMDLINE_ADDR 0x003ff000 #define CMDLINE_ADDR 0x003ff000
#define PROM_SIZE_MAX (4 * 1024 * 1024) #define PROM_SIZE_MAX (4 * MiB)
#define PROM_VADDR 0x000ffd00000ULL #define PROM_VADDR 0x000ffd00000ULL
#define PBM_SPECIAL_BASE 0x1fe00000000ULL #define PBM_SPECIAL_BASE 0x1fe00000000ULL
#define PBM_MEM_BASE 0x1ff00000000ULL #define PBM_MEM_BASE 0x1ff00000000ULL

13
hw/tricore/tricore_testboard.c
View File

@ -19,6 +19,7 @@
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "cpu.h" #include "cpu.h"
@ -72,17 +73,17 @@ static void tricore_testboard_init(MachineState *machine, int board_id)
cpu = TRICORE_CPU(cpu_create(machine->cpu_type)); cpu = TRICORE_CPU(cpu_create(machine->cpu_type));
env = &cpu->env; env = &cpu->env;
memory_region_init_ram(ext_cram, NULL, "powerlink_ext_c.ram", memory_region_init_ram(ext_cram, NULL, "powerlink_ext_c.ram",
2 * 1024 * 1024, &error_fatal); 2 * MiB, &error_fatal);
memory_region_init_ram(ext_dram, NULL, "powerlink_ext_d.ram", memory_region_init_ram(ext_dram, NULL, "powerlink_ext_d.ram",
4 * 1024 * 1024, &error_fatal); 4 * MiB, &error_fatal);
memory_region_init_ram(int_cram, NULL, "powerlink_int_c.ram", 48 * 1024, memory_region_init_ram(int_cram, NULL, "powerlink_int_c.ram", 48 * KiB,
&error_fatal); &error_fatal);
memory_region_init_ram(int_dram, NULL, "powerlink_int_d.ram", 48 * 1024, memory_region_init_ram(int_dram, NULL, "powerlink_int_d.ram", 48 * KiB,
&error_fatal); &error_fatal);
memory_region_init_ram(pcp_data, NULL, "powerlink_pcp_data.ram", memory_region_init_ram(pcp_data, NULL, "powerlink_pcp_data.ram",
16 * 1024, &error_fatal); 16 * KiB, &error_fatal);
memory_region_init_ram(pcp_text, NULL, "powerlink_pcp_text.ram", memory_region_init_ram(pcp_text, NULL, "powerlink_pcp_text.ram",
32 * 1024, &error_fatal); 32 * KiB, &error_fatal);
memory_region_add_subregion(sysmem, 0x80000000, ext_cram); memory_region_add_subregion(sysmem, 0x80000000, ext_cram);
memory_region_add_subregion(sysmem, 0xa1000000, ext_dram); memory_region_add_subregion(sysmem, 0xa1000000, ext_dram);

9
hw/usb/ccid-card-passthru.c
View File

@ -9,6 +9,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include <libcacard.h> #include <libcacard.h>
#include "chardev/char-fe.h" #include "chardev/char-fe.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
@ -40,7 +41,7 @@ static const uint8_t DEFAULT_ATR[] = {
0x13, 0x08 0x13, 0x08
}; };
#define VSCARD_IN_SIZE 65536 #define VSCARD_IN_SIZE (64 * KiB)
/* maximum size of ATR - from 7816-3 */ /* maximum size of ATR - from 7816-3 */
#define MAX_ATR_SIZE 40 #define MAX_ATR_SIZE 40
@ -275,9 +276,9 @@ static void ccid_card_vscard_read(void *opaque, const uint8_t *buf, int size)
VSCMsgHeader *hdr; VSCMsgHeader *hdr;
if (card->vscard_in_pos + size > VSCARD_IN_SIZE) { if (card->vscard_in_pos + size > VSCARD_IN_SIZE) {
error_report( error_report("no room for data: pos %u + size %d > %" PRId64 "."
"no room for data: pos %d + size %d > %d. dropping connection.", " dropping connection.",
card->vscard_in_pos, size, VSCARD_IN_SIZE); card->vscard_in_pos, size, VSCARD_IN_SIZE);
ccid_card_vscard_drop_connection(card); ccid_card_vscard_drop_connection(card);
return; return;
} }

3
hw/usb/combined-packet.c
View File

@ -20,6 +20,7 @@
* along with this program; if not, see <http://www.gnu.org/licenses/>. * along with this program; if not, see <http://www.gnu.org/licenses/>.
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "hw/usb.h" #include "hw/usb.h"
#include "qemu/iov.h" #include "qemu/iov.h"
@ -171,7 +172,7 @@ void usb_ep_combine_input_packets(USBEndpoint *ep)
if ((p->iov.size % ep->max_packet_size) != 0 || !p->short_not_ok || if ((p->iov.size % ep->max_packet_size) != 0 || !p->short_not_ok ||
next == NULL || next == NULL ||
/* Work around for Linux usbfs bulk splitting + migration */ /* Work around for Linux usbfs bulk splitting + migration */
(totalsize == 16348 && p->int_req)) { (totalsize == (16 * KiB - 36) && p->int_req)) {
usb_device_handle_data(ep->dev, first); usb_device_handle_data(ep->dev, first);
assert(first->status == USB_RET_ASYNC); assert(first->status == USB_RET_ASYNC);
if (first->combined) { if (first->combined) {

3
hw/usb/dev-smartcard-reader.c
View File

@ -35,6 +35,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
@ -63,7 +64,7 @@ do { \
* or handle the migration complexity - VMState doesn't handle this case. * or handle the migration complexity - VMState doesn't handle this case.
* sizes are expected never to be exceeded, unless guest misbehaves. * sizes are expected never to be exceeded, unless guest misbehaves.
*/ */
#define BULK_OUT_DATA_SIZE 65536 #define BULK_OUT_DATA_SIZE (64 * KiB)
#define PENDING_ANSWERS_NUM 128 #define PENDING_ANSWERS_NUM 128
#define BULK_IN_BUF_SIZE 384 #define BULK_IN_BUF_SIZE 384

3
hw/usb/redirect.c
View File

@ -26,6 +26,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "qemu/timer.h" #include "qemu/timer.h"
@ -1298,7 +1299,7 @@ static int usbredir_chardev_can_read(void *opaque)
} }
/* usbredir_parser_do_read will consume *all* data we give it */ /* usbredir_parser_do_read will consume *all* data we give it */
return 1024 * 1024; return 1 * MiB;
} }
static void usbredir_chardev_read(void *opaque, const uint8_t *buf, int size) static void usbredir_chardev_read(void *opaque, const uint8_t *buf, int size)

9
hw/vfio/pci-quirks.c
View File

@ -11,6 +11,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
#include "qemu/main-loop.h" #include "qemu/main-loop.h"
#include "qemu/range.h" #include "qemu/range.h"
@ -1448,9 +1449,9 @@ static int vfio_igd_gtt_max(VFIOPCIDevice *vdev)
ggms = 1 << ggms; ggms = 1 << ggms;
} }
ggms *= 1024 * 1024; ggms *= MiB;
return (ggms / (4 * 1024)) * (gen < 8 ? 4 : 8); return (ggms / (4 * KiB)) * (gen < 8 ? 4 : 8);
} }
/* /*
@ -1705,7 +1706,7 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, int nr)
igd->vdev = vdev; igd->vdev = vdev;
igd->index = ~0; igd->index = ~0;
igd->bdsm = vfio_pci_read_config(&vdev->pdev, IGD_BDSM, 4); igd->bdsm = vfio_pci_read_config(&vdev->pdev, IGD_BDSM, 4);
igd->bdsm &= ~((1 << 20) - 1); /* 1MB aligned */ igd->bdsm &= ~((1 * MiB) - 1); /* 1MB aligned */
memory_region_init_io(&quirk->mem[0], OBJECT(vdev), &vfio_igd_index_quirk, memory_region_init_io(&quirk->mem[0], OBJECT(vdev), &vfio_igd_index_quirk,
igd, "vfio-igd-index-quirk", 4); igd, "vfio-igd-index-quirk", 4);
@ -1752,7 +1753,7 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, int nr)
* config offset 0x5C. * config offset 0x5C.
*/ */
bdsm_size = g_malloc(sizeof(*bdsm_size)); bdsm_size = g_malloc(sizeof(*bdsm_size));
*bdsm_size = cpu_to_le64((ggms_mb + gms_mb) * 1024 * 1024); *bdsm_size = cpu_to_le64((ggms_mb + gms_mb) * MiB);
fw_cfg_add_file(fw_cfg_find(), "etc/igd-bdsm-size", fw_cfg_add_file(fw_cfg_find(), "etc/igd-bdsm-size",
bdsm_size, sizeof(*bdsm_size)); bdsm_size, sizeof(*bdsm_size));

3
hw/vfio/pci.c
View File

@ -28,6 +28,7 @@
#include "qemu/error-report.h" #include "qemu/error-report.h"
#include "qemu/option.h" #include "qemu/option.h"
#include "qemu/range.h" #include "qemu/range.h"
#include "qemu/units.h"
#include "sysemu/kvm.h" #include "sysemu/kvm.h"
#include "sysemu/sysemu.h" #include "sysemu/sysemu.h"
#include "pci.h" #include "pci.h"
@ -1417,7 +1418,7 @@ static void vfio_pci_relocate_msix(VFIOPCIDevice *vdev, Error **errp)
} }
/* 2GB max size for 32-bit BARs, cannot double if already > 1G */ /* 2GB max size for 32-bit BARs, cannot double if already > 1G */
if (vdev->bars[target_bar].size > (1 * 1024 * 1024 * 1024) && if (vdev->bars[target_bar].size > 1 * GiB &&
!vdev->bars[target_bar].mem64) { !vdev->bars[target_bar].mem64) {
error_setg(errp, "Invalid MSI-X relocation BAR %d, " error_setg(errp, "Invalid MSI-X relocation BAR %d, "
"no space to extend 32-bit BAR", target_bar); "no space to extend 32-bit BAR", target_bar);

13
hw/xenpv/xen_domainbuild.c
View File

@ -1,4 +1,5 @@
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/xen/xen_backend.h" #include "hw/xen/xen_backend.h"
#include "xen_domainbuild.h" #include "xen_domainbuild.h"
#include "qemu/timer.h" #include "qemu/timer.h"
@ -75,9 +76,9 @@ int xenstore_domain_init1(const char *kernel, const char *ramdisk,
xenstore_write_str(dom, "vm", vm); xenstore_write_str(dom, "vm", vm);
/* memory */ /* memory */
xenstore_write_int(dom, "memory/target", ram_size >> 10); // kB xenstore_write_int(dom, "memory/target", ram_size / KiB);
xenstore_write_int(vm, "memory", ram_size >> 20); // MB xenstore_write_int(vm, "memory", ram_size / MiB);
xenstore_write_int(vm, "maxmem", ram_size >> 20); // MB xenstore_write_int(vm, "maxmem", ram_size / MiB);
/* cpus */ /* cpus */
for (i = 0; i < smp_cpus; i++) { for (i = 0; i < smp_cpus; i++) {
@ -113,7 +114,7 @@ int xenstore_domain_init2(int xenstore_port, int xenstore_mfn,
/* console */ /* console */
xenstore_write_str(dom, "console/type", "ioemu"); xenstore_write_str(dom, "console/type", "ioemu");
xenstore_write_int(dom, "console/limit", 128 * 1024); xenstore_write_int(dom, "console/limit", 128 * KiB);
xenstore_write_int(dom, "console/ring-ref", console_mfn); xenstore_write_int(dom, "console/ring-ref", console_mfn);
xenstore_write_int(dom, "console/port", console_port); xenstore_write_int(dom, "console/port", console_port);
xen_config_dev_console(0); xen_config_dev_console(0);
@ -260,7 +261,7 @@ int xen_domain_build_pv(const char *kernel, const char *ramdisk,
} }
#endif #endif
rc = xc_domain_setmaxmem(xen_xc, xen_domid, ram_size >> 10); rc = xc_domain_setmaxmem(xen_xc, xen_domid, ram_size / KiB);
if (rc < 0) { if (rc < 0) {
fprintf(stderr, "xen: xc_domain_setmaxmem() failed\n"); fprintf(stderr, "xen: xc_domain_setmaxmem() failed\n");
goto err; goto err;
@ -269,7 +270,7 @@ int xen_domain_build_pv(const char *kernel, const char *ramdisk,
xenstore_port = xc_evtchn_alloc_unbound(xen_xc, xen_domid, 0); xenstore_port = xc_evtchn_alloc_unbound(xen_xc, xen_domid, 0);
console_port = xc_evtchn_alloc_unbound(xen_xc, xen_domid, 0); console_port = xc_evtchn_alloc_unbound(xen_xc, xen_domid, 0);
rc = xc_linux_build(xen_xc, xen_domid, ram_size >> 20, rc = xc_linux_build(xen_xc, xen_domid, ram_size / MiB,
kernel, ramdisk, cmdline, kernel, ramdisk, cmdline,
0, flags, 0, flags,
xenstore_port, &xenstore_mfn, xenstore_port, &xenstore_mfn,

9
hw/xtensa/xtfpga.c
View File

@ -26,6 +26,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "cpu.h" #include "cpu.h"
#include "sysemu/sysemu.h" #include "sysemu/sysemu.h"
@ -152,7 +153,7 @@ static void xtfpga_net_init(MemoryRegion *address_space,
sysbus_mmio_get_region(s, 1)); sysbus_mmio_get_region(s, 1));
ram = g_malloc(sizeof(*ram)); ram = g_malloc(sizeof(*ram));
memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16384, memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16 * KiB,
&error_fatal); &error_fatal);
vmstate_register_ram_global(ram); vmstate_register_ram_global(ram);
memory_region_add_subregion(address_space, buffers, ram); memory_region_add_subregion(address_space, buffers, ram);
@ -229,7 +230,7 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
const char *kernel_cmdline = qemu_opt_get(machine_opts, "append"); const char *kernel_cmdline = qemu_opt_get(machine_opts, "append");
const char *dtb_filename = qemu_opt_get(machine_opts, "dtb"); const char *dtb_filename = qemu_opt_get(machine_opts, "dtb");
const char *initrd_filename = qemu_opt_get(machine_opts, "initrd"); const char *initrd_filename = qemu_opt_get(machine_opts, "initrd");
const unsigned system_io_size = 224 * 1024 * 1024; const unsigned system_io_size = 224 * MiB;
int n; int n;
for (n = 0; n < smp_cpus; n++) { for (n = 0; n < smp_cpus; n++) {
@ -342,7 +343,7 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
cpu_physical_memory_write(cur_lowmem, fdt, fdt_size); cpu_physical_memory_write(cur_lowmem, fdt, fdt_size);
cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT, cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT,
sizeof(dtb_addr), &dtb_addr); sizeof(dtb_addr), &dtb_addr);
cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4096); cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4 * KiB);
} }
#else #else
if (dtb_filename) { if (dtb_filename) {
@ -370,7 +371,7 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
initrd_location.end = tswap32(cur_lowmem + initrd_size); initrd_location.end = tswap32(cur_lowmem + initrd_size);
cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD, cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD,
sizeof(initrd_location), &initrd_location); sizeof(initrd_location), &initrd_location);
cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4096); cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4 * KiB);
} }
cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL); cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL);
env->regs[2] = tagptr; env->regs[2] = tagptr;

8
include/exec/exec-all.h
View File

@ -412,13 +412,11 @@ static inline uint32_t curr_cflags(void)
} }
/* TranslationBlock invalidate API */ /* TranslationBlock invalidate API */
#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
#else
void tb_invalidate_phys_addr(target_ulong addr);
#endif
#if defined(CONFIG_USER_ONLY) #if defined(CONFIG_USER_ONLY)
void tb_invalidate_phys_addr(target_ulong addr);
void tb_invalidate_phys_range(target_ulong start, target_ulong end); void tb_invalidate_phys_range(target_ulong start, target_ulong end);
#else
void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
#endif #endif
void tb_flush(CPUState *cpu); void tb_flush(CPUState *cpu);
void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);

3
include/hw/acpi/tpm.h
View File

@ -16,6 +16,7 @@
#ifndef HW_ACPI_TPM_H #ifndef HW_ACPI_TPM_H
#define HW_ACPI_TPM_H #define HW_ACPI_TPM_H
#include "qemu/units.h"
#include "hw/registerfields.h" #include "hw/registerfields.h"
#define TPM_TIS_ADDR_BASE 0xFED40000 #define TPM_TIS_ADDR_BASE 0xFED40000
@ -176,7 +177,7 @@ REG32(CRB_DATA_BUFFER, 0x80)
#define TPM_CRB_ADDR_CTRL (TPM_CRB_ADDR_BASE + A_CRB_CTRL_REQ) #define TPM_CRB_ADDR_CTRL (TPM_CRB_ADDR_BASE + A_CRB_CTRL_REQ)
#define TPM_CRB_R_MAX R_CRB_DATA_BUFFER #define TPM_CRB_R_MAX R_CRB_DATA_BUFFER
#define TPM_LOG_AREA_MINIMUM_SIZE (64 * 1024) #define TPM_LOG_AREA_MINIMUM_SIZE (64 * KiB)
#define TPM_TCPA_ACPI_CLASS_CLIENT 0 #define TPM_TCPA_ACPI_CLASS_CLIENT 0
#define TPM_TCPA_ACPI_CLASS_SERVER 1 #define TPM_TCPA_ACPI_CLASS_SERVER 1

5
include/hw/display/xlnx_dp.h
View File

@ -29,14 +29,15 @@
#include "hw/display/dpcd.h" #include "hw/display/dpcd.h"
#include "hw/i2c/i2c-ddc.h" #include "hw/i2c/i2c-ddc.h"
#include "qemu/fifo8.h" #include "qemu/fifo8.h"
#include "qemu/units.h"
#include "hw/dma/xlnx_dpdma.h" #include "hw/dma/xlnx_dpdma.h"
#include "audio/audio.h" #include "audio/audio.h"
#ifndef XLNX_DP_H #ifndef XLNX_DP_H
#define XLNX_DP_H #define XLNX_DP_H
#define AUD_CHBUF_MAX_DEPTH 32768 #define AUD_CHBUF_MAX_DEPTH (32 * KiB)
#define MAX_QEMU_BUFFER_SIZE 4096 #define MAX_QEMU_BUFFER_SIZE (4 * KiB)
#define DP_CORE_REG_ARRAY_SIZE (0x3AF >> 2) #define DP_CORE_REG_ARRAY_SIZE (0x3AF >> 2)
#define DP_AVBUF_REG_ARRAY_SIZE (0x238 >> 2) #define DP_AVBUF_REG_ARRAY_SIZE (0x238 >> 2)

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