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target-arm: add MVBAR support 

Use MVBAR register as exception vector base address for
exceptions taken to CPU monitor mode.

Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com>
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1416242878-876-13-git-send-email-greg.bellows@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Fabian Aggeler 2014-12-11 12:07:50 +00:00 committed by Peter Maydell
parent 144634ae6c
commit e89e51a17e
2 changed files with 10 additions and 6 deletions
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1
target-arm/cpu.h
View File

@ -211,6 +211,7 @@ typedef struct CPUARMState {
uint32_t c9_pminten; /* perf monitor interrupt enables */ uint32_t c9_pminten; /* perf monitor interrupt enables */
uint64_t mair_el1; uint64_t mair_el1;
uint64_t vbar_el[4]; /* vector base address register */ uint64_t vbar_el[4]; /* vector base address register */
uint32_t mvbar; /* (monitor) vector base address register */
uint32_t c13_fcse; /* FCSE PID. */ uint32_t c13_fcse; /* FCSE PID. */
uint64_t contextidr_el1; /* Context ID. */ uint64_t contextidr_el1; /* Context ID. */
uint64_t tpidr_el0; /* User RW Thread register. */ uint64_t tpidr_el0; /* User RW Thread register. */

15
target-arm/helper.c
View File

@ -2356,6 +2356,9 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
{ .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
.access = PL3_W | PL1_R, .resetvalue = 0, .access = PL3_W | PL1_R, .resetvalue = 0,
.fieldoffset = offsetof(CPUARMState, cp15.nsacr) }, .fieldoffset = offsetof(CPUARMState, cp15.nsacr) },
{ .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
.access = PL3_RW, .writefn = vbar_write, .resetvalue = 0,
.fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
REGINFO_SENTINEL REGINFO_SENTINEL
}; };
@ -4272,16 +4275,16 @@ void arm_cpu_do_interrupt(CPUState *cs)
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
return; /* Never happens. Keep compiler happy. */ return; /* Never happens. Keep compiler happy. */
} }
/* High vectors. */
if (env->cp15.c1_sys & SCTLR_V) { if (new_mode == ARM_CPU_MODE_MON) {
/* when enabled, base address cannot be remapped. */ addr += env->cp15.mvbar;
} else if (env->cp15.c1_sys & SCTLR_V) {
/* High vectors. When enabled, base address cannot be remapped. */
addr += 0xffff0000; addr += 0xffff0000;
} else { } else {
/* ARM v7 architectures provide a vector base address register to remap /* ARM v7 architectures provide a vector base address register to remap
* the interrupt vector table. * the interrupt vector table.
* This register is only followed in non-monitor mode, and has a secure * This register is only followed in non-monitor mode, and is banked.
* and un-secure copy. Since the cpu is always in a un-secure operation
* and is never in monitor mode this feature is always active.
* Note: only bits 31:5 are valid. * Note: only bits 31:5 are valid.
*/ */
addr += env->cp15.vbar_el[1]; addr += env->cp15.vbar_el[1];