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ARM half word load/store fix (Ulrich Hecht) 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@438 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard 2003-11-03 22:25:25 +00:00
parent b8ed223bfe
commit e748ba4f53
1 changed files with 3 additions and 2 deletions
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5
target-arm/translate.c
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@ -546,8 +546,7 @@ static void disas_arm_insn(DisasContext *s)
rn = (insn >> 16) & 0xf; rn = (insn >> 16) & 0xf;
rd = (insn >> 12) & 0xf; rd = (insn >> 12) & 0xf;
gen_movl_T1_reg(s, rn); gen_movl_T1_reg(s, rn);
if (insn & (1 << 25)) gen_add_datah_offset(s, insn);
gen_add_datah_offset(s, insn);
if (insn & (1 << 20)) { if (insn & (1 << 20)) {
/* load */ /* load */
switch(sh) { switch(sh) {
@ -562,8 +561,10 @@ static void disas_arm_insn(DisasContext *s)
gen_op_ldsw_T0_T1(); gen_op_ldsw_T0_T1();
break; break;
} }
gen_movl_reg_T0(s, rd);
} else { } else {
/* store */ /* store */
gen_movl_T0_reg(s, rd);
gen_op_stw_T0_T1(); gen_op_stw_T0_T1();
} }
if (!(insn & (1 << 24))) { if (!(insn & (1 << 24))) {