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ppc: spelling fixes 

Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Michael Tokarev 2023-07-14 14:18:16 +03:00
parent 4907644841
commit e6a19a6477
15 changed files with 30 additions and 30 deletions
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2
host/include/ppc/host/cpuinfo.h
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@ -1,6 +1,6 @@
/* /*
* SPDX-License-Identifier: GPL-2.0-or-later * SPDX-License-Identifier: GPL-2.0-or-later
* Host specific cpu indentification for ppc. * Host specific cpu identification for ppc.
*/ */
#ifndef HOST_CPUINFO_H #ifndef HOST_CPUINFO_H

2
hw/ppc/ppc.c
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@ -738,7 +738,7 @@ static target_ulong _cpu_ppc_load_decr(CPUPPCState *env, int64_t now)
decr = __cpu_ppc_load_decr(env, now, tb_env->decr_next); decr = __cpu_ppc_load_decr(env, now, tb_env->decr_next);
/* /*
* If large decrementer is enabled then the decrementer is signed extened * If large decrementer is enabled then the decrementer is signed extended
* to 64 bits, otherwise it is a 32 bit value. * to 64 bits, otherwise it is a 32 bit value.
*/ */
if (env->spr[SPR_LPCR] & LPCR_LD) { if (env->spr[SPR_LPCR] & LPCR_LD) {

2
hw/ppc/prep_systemio.c
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@ -39,7 +39,7 @@
#define TYPE_PREP_SYSTEMIO "prep-systemio" #define TYPE_PREP_SYSTEMIO "prep-systemio"
OBJECT_DECLARE_SIMPLE_TYPE(PrepSystemIoState, PREP_SYSTEMIO) OBJECT_DECLARE_SIMPLE_TYPE(PrepSystemIoState, PREP_SYSTEMIO)
/* Bit as defined in PowerPC Reference Plaform v1.1, sect. 6.1.5, p. 132 */ /* Bit as defined in PowerPC Reference Platform v1.1, sect. 6.1.5, p. 132 */
#define PREP_BIT(n) (1 << (7 - (n))) #define PREP_BIT(n) (1 << (7 - (n)))
struct PrepSystemIoState { struct PrepSystemIoState {

8
hw/ppc/spapr.c
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@ -2573,7 +2573,7 @@ static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp)
return; return;
} }
/* Detemine the VSMT mode to use: */ /* Determine the VSMT mode to use: */
if (vsmt_user) { if (vsmt_user) {
if (spapr->vsmt < smp_threads) { if (spapr->vsmt < smp_threads) {
error_setg(errp, "Cannot support VSMT mode %d" error_setg(errp, "Cannot support VSMT mode %d"
@ -3107,7 +3107,7 @@ static int spapr_kvm_type(MachineState *machine, const char *vm_type)
{ {
/* /*
* The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to
* accomodate the 'HV' and 'PV' formats that exists in the * accommodate the 'HV' and 'PV' formats that exists in the
* wild. The 'auto' mode is being introduced already as * wild. The 'auto' mode is being introduced already as
* lower-case, thus we don't need to bother checking for * lower-case, thus we don't need to bother checking for
* "AUTO". * "AUTO".
@ -4340,7 +4340,7 @@ spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index)
CPUArchId *core_slot; CPUArchId *core_slot;
MachineClass *mc = MACHINE_GET_CLASS(machine); MachineClass *mc = MACHINE_GET_CLASS(machine);
/* make sure possible_cpu are intialized */ /* make sure possible_cpu are initialized */
mc->possible_cpu_arch_ids(machine); mc->possible_cpu_arch_ids(machine);
/* get CPU core slot containing thread that matches cpu_index */ /* get CPU core slot containing thread that matches cpu_index */
core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL);
@ -5034,7 +5034,7 @@ static void spapr_machine_2_12_class_options(MachineClass *mc)
/* We depend on kvm_enabled() to choose a default value for the /* We depend on kvm_enabled() to choose a default value for the
* hpt-max-page-size capability. Of course we can't do it here * hpt-max-page-size capability. Of course we can't do it here
* because this is too early and the HW accelerator isn't initialzed * because this is too early and the HW accelerator isn't initialized
* yet. Postpone this to machine init (see default_caps_with_cpu()). * yet. Postpone this to machine init (see default_caps_with_cpu()).
*/ */
smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0;

2
hw/ppc/spapr_hcall.c
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@ -1615,7 +1615,7 @@ static void hypercall_register_types(void)
spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS, spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS,
h_get_cpu_characteristics); h_get_cpu_characteristics);
/* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate /* "debugger" hcalls (also used by SLOF). Note: We do -not- differentiate
* here between the "CI" and the "CACHE" variants, they will use whatever * here between the "CI" and the "CACHE" variants, they will use whatever
* mapping attributes qemu is using. When using KVM, the kernel will * mapping attributes qemu is using. When using KVM, the kernel will
* enforce the attributes more strongly * enforce the attributes more strongly

4
hw/ppc/spapr_nvdimm.c
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@ -378,7 +378,7 @@ static target_ulong h_scm_bind_mem(PowerPCCPU *cpu, SpaprMachineState *spapr,
/* /*
* Currently continue token should be zero qemu has already bound * Currently continue token should be zero qemu has already bound
* everything and this hcall doesnt return H_BUSY. * everything and this hcall doesn't return H_BUSY.
*/ */
if (continue_token > 0) { if (continue_token > 0) {
return H_P5; return H_P5;
@ -589,7 +589,7 @@ void spapr_nvdimm_finish_flushes(void)
* Called on reset path, the main loop thread which calls * Called on reset path, the main loop thread which calls
* the pending BHs has gotten out running in the reset path, * the pending BHs has gotten out running in the reset path,
* finally reaching here. Other code path being guest * finally reaching here. Other code path being guest
* h_client_architecture_support, thats early boot up. * h_client_architecture_support, that's early boot up.
*/ */
nvdimms = nvdimm_get_device_list(); nvdimms = nvdimm_get_device_list();
for (list = nvdimms; list; list = list->next) { for (list = nvdimms; list; list = list->next) {

2
hw/ppc/spapr_pci_vfio.c
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@ -78,7 +78,7 @@ int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb,
* call. Now we just need to check the validity of the PCI * call. Now we just need to check the validity of the PCI
* pass-through devices (vfio-pci) under this sphb bus. * pass-through devices (vfio-pci) under this sphb bus.
* We have already validated that all the devices under this sphb * We have already validated that all the devices under this sphb
* are from same iommu group (within same PE) before comming here. * are from same iommu group (within same PE) before coming here.
* *
* Prior to linux commit 98ba956f6a389 ("powerpc/pseries/eeh: * Prior to linux commit 98ba956f6a389 ("powerpc/pseries/eeh:
* Rework device EEH PE determination") kernel would call * Rework device EEH PE determination") kernel would call

2
include/hw/ppc/openpic.h
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@ -14,7 +14,7 @@ enum {
OPENPIC_OUTPUT_INT = 0, /* IRQ */ OPENPIC_OUTPUT_INT = 0, /* IRQ */
OPENPIC_OUTPUT_CINT, /* critical IRQ */ OPENPIC_OUTPUT_CINT, /* critical IRQ */
OPENPIC_OUTPUT_MCK, /* Machine check event */ OPENPIC_OUTPUT_MCK, /* Machine check event */
OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */ OPENPIC_OUTPUT_DEBUG, /* Unconditional debug event */
OPENPIC_OUTPUT_RESET, /* Core reset event */ OPENPIC_OUTPUT_RESET, /* Core reset event */
OPENPIC_OUTPUT_NB, OPENPIC_OUTPUT_NB,
}; };

2
include/hw/ppc/spapr.h
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@ -193,7 +193,7 @@ struct SpaprMachineState {
SpaprResizeHpt resize_hpt; SpaprResizeHpt resize_hpt;
void *htab; void *htab;
uint32_t htab_shift; uint32_t htab_shift;
uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROC_TBL */ uint64_t patb_entry; /* Process tbl registered in H_REGISTER_PROC_TBL */
SpaprPendingHpt *pending_hpt; /* in-progress resize */ SpaprPendingHpt *pending_hpt; /* in-progress resize */
hwaddr rma_size; hwaddr rma_size;

4
target/ppc/cpu-models.h
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@ -44,7 +44,7 @@ enum {
/* PowerPC 405 cores */ /* PowerPC 405 cores */
CPU_POWERPC_405D2 = 0x20010000, CPU_POWERPC_405D2 = 0x20010000,
CPU_POWERPC_405D4 = 0x41810000, CPU_POWERPC_405D4 = 0x41810000,
/* PowerPC 405 microcontrolers */ /* PowerPC 405 microcontrollers */
/* XXX: missing 0x200108a0 */ /* XXX: missing 0x200108a0 */
CPU_POWERPC_405CRa = 0x40110041, CPU_POWERPC_405CRa = 0x40110041,
CPU_POWERPC_405CRb = 0x401100C5, CPU_POWERPC_405CRb = 0x401100C5,
@ -74,7 +74,7 @@ enum {
#define CPU_POWERPC_440 CPU_POWERPC_440GXf #define CPU_POWERPC_440 CPU_POWERPC_440GXf
/* PowerPC 440 cores */ /* PowerPC 440 cores */
CPU_POWERPC_440_XILINX = 0x7ff21910, CPU_POWERPC_440_XILINX = 0x7ff21910,
/* PowerPC 440 microcontrolers */ /* PowerPC 440 microcontrollers */
CPU_POWERPC_440EPa = 0x42221850, CPU_POWERPC_440EPa = 0x42221850,
CPU_POWERPC_440EPb = 0x422218D3, CPU_POWERPC_440EPb = 0x422218D3,
CPU_POWERPC_440GPb = 0x40120440, CPU_POWERPC_440GPb = 0x40120440,

2
target/ppc/cpu.h
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@ -428,7 +428,7 @@ FIELD(MSR, LE, MSR_LE, 1)
/* PMU bits */ /* PMU bits */
#define MMCR0_FC PPC_BIT(32) /* Freeze Counters */ #define MMCR0_FC PPC_BIT(32) /* Freeze Counters */
#define MMCR0_PMAO PPC_BIT(56) /* Perf Monitor Alert Ocurred */ #define MMCR0_PMAO PPC_BIT(56) /* Perf Monitor Alert Occurred */
#define MMCR0_PMAE PPC_BIT(37) /* Perf Monitor Alert Enable */ #define MMCR0_PMAE PPC_BIT(37) /* Perf Monitor Alert Enable */
#define MMCR0_EBE PPC_BIT(43) /* Perf Monitor EBB Enable */ #define MMCR0_EBE PPC_BIT(43) /* Perf Monitor EBB Enable */
#define MMCR0_FCECE PPC_BIT(38) /* FC on Enabled Cond or Event */ #define MMCR0_FCECE PPC_BIT(38) /* FC on Enabled Cond or Event */

4
target/ppc/cpu_init.c
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@ -5347,7 +5347,7 @@ static void register_970_lpar_sprs(CPUPPCState *env)
static void register_power5p_lpar_sprs(CPUPPCState *env) static void register_power5p_lpar_sprs(CPUPPCState *env)
{ {
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
/* Logical partitionning */ /* Logical partitioning */
spr_register_kvm_hv(env, SPR_LPCR, "LPCR", spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS,
@ -5760,7 +5760,7 @@ static void register_power9_mmu_sprs(CPUPPCState *env)
static void register_power10_hash_sprs(CPUPPCState *env) static void register_power10_hash_sprs(CPUPPCState *env)
{ {
/* /*
* it's the OS responsability to generate a random value for the registers * it's the OS responsibility to generate a random value for the registers
* in each process' context. So, initialize it with 0 here. * in each process' context. So, initialize it with 0 here.
*/ */
uint64_t hashkeyr_initial_value = 0, hashpkeyr_initial_value = 0; uint64_t hashkeyr_initial_value = 0, hashpkeyr_initial_value = 0;

12
target/ppc/excp_helper.c
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@ -455,7 +455,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
/* /*
* new interrupt handler msr preserves existing ME unless * new interrupt handler msr preserves existing ME unless
* explicitly overriden. * explicitly overridden.
*/ */
new_msr = env->msr & (((target_ulong)1 << MSR_ME)); new_msr = env->msr & (((target_ulong)1 << MSR_ME));
@ -578,7 +578,7 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
/* /*
* new interrupt handler msr preserves existing ME unless * new interrupt handler msr preserves existing ME unless
* explicitly overriden * explicitly overridden
*/ */
new_msr = env->msr & ((target_ulong)1 << MSR_ME); new_msr = env->msr & ((target_ulong)1 << MSR_ME);
@ -739,7 +739,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
/* /*
* new interrupt handler msr preserves existing ME unless * new interrupt handler msr preserves existing ME unless
* explicitly overriden * explicitly overridden
*/ */
new_msr = env->msr & ((target_ulong)1 << MSR_ME); new_msr = env->msr & ((target_ulong)1 << MSR_ME);
@ -911,7 +911,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
/* /*
* new interrupt handler msr preserves existing ME unless * new interrupt handler msr preserves existing ME unless
* explicitly overriden * explicitly overridden
*/ */
new_msr = env->msr & ((target_ulong)1 << MSR_ME); new_msr = env->msr & ((target_ulong)1 << MSR_ME);
@ -1075,7 +1075,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
/* /*
* new interrupt handler msr preserves existing ME unless * new interrupt handler msr preserves existing ME unless
* explicitly overriden * explicitly overridden
*/ */
new_msr = env->msr & ((target_ulong)1 << MSR_ME); new_msr = env->msr & ((target_ulong)1 << MSR_ME);
@ -1377,7 +1377,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
/* /*
* new interrupt handler msr preserves existing HV and ME unless * new interrupt handler msr preserves existing HV and ME unless
* explicitly overriden * explicitly overridden
*/ */
new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB); new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);

4
target/ppc/power8-pmu-regs.c.inc
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@ -16,7 +16,7 @@
* Checks whether the Group A SPR (MMCR0, MMCR2, MMCRA, and the * Checks whether the Group A SPR (MMCR0, MMCR2, MMCRA, and the
* PMCs) has problem state read access. * PMCs) has problem state read access.
* *
* Read acccess is granted for all PMCC values but 0b01, where a * Read access is granted for all PMCC values but 0b01, where a
* Facility Unavailable Interrupt will occur. * Facility Unavailable Interrupt will occur.
*/ */
static bool spr_groupA_read_allowed(DisasContext *ctx) static bool spr_groupA_read_allowed(DisasContext *ctx)
@ -33,7 +33,7 @@ static bool spr_groupA_read_allowed(DisasContext *ctx)
* Checks whether the Group A SPR (MMCR0, MMCR2, MMCRA, and the * Checks whether the Group A SPR (MMCR0, MMCR2, MMCRA, and the
* PMCs) has problem state write access. * PMCs) has problem state write access.
* *
* Write acccess is granted for PMCC values 0b10 and 0b11. Userspace * Write access is granted for PMCC values 0b10 and 0b11. Userspace
* writing with PMCC 0b00 will generate a Hypervisor Emulation * writing with PMCC 0b00 will generate a Hypervisor Emulation
* Assistance Interrupt. Userspace writing with PMCC 0b01 will * Assistance Interrupt. Userspace writing with PMCC 0b01 will
* generate a Facility Unavailable Interrupt. * generate a Facility Unavailable Interrupt.

6
target/ppc/translate/vmx-impl.c.inc
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@ -119,7 +119,7 @@ static void gen_stve##name(DisasContext *ctx) \
} }
GEN_VR_LDX(lvx, 0x07, 0x03); GEN_VR_LDX(lvx, 0x07, 0x03);
/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */ /* As we don't emulate the cache, lvxl is strictly equivalent to lvx */
GEN_VR_LDX(lvxl, 0x07, 0x0B); GEN_VR_LDX(lvxl, 0x07, 0x0B);
GEN_VR_LVE(bx, 0x07, 0x00, 1); GEN_VR_LVE(bx, 0x07, 0x00, 1);
@ -127,7 +127,7 @@ GEN_VR_LVE(hx, 0x07, 0x01, 2);
GEN_VR_LVE(wx, 0x07, 0x02, 4); GEN_VR_LVE(wx, 0x07, 0x02, 4);
GEN_VR_STX(svx, 0x07, 0x07); GEN_VR_STX(svx, 0x07, 0x07);
/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ /* As we don't emulate the cache, stvxl is strictly equivalent to stvx */
GEN_VR_STX(svxl, 0x07, 0x0F); GEN_VR_STX(svxl, 0x07, 0x0F);
GEN_VR_STVE(bx, 0x07, 0x04, 1); GEN_VR_STVE(bx, 0x07, 0x04, 1);
@ -1526,7 +1526,7 @@ static void gen_vprtyb_vec(unsigned vece, TCGv_vec t, TCGv_vec b)
{ {
int i; int i;
TCGv_vec tmp = tcg_temp_new_vec_matching(b); TCGv_vec tmp = tcg_temp_new_vec_matching(b);
/* MO_32 is 2, so 2 iteractions for MO_32 and 3 for MO_64 */ /* MO_32 is 2, so 2 iterations for MO_32 and 3 for MO_64 */
for (i = 0; i < vece; i++) { for (i = 0; i < vece; i++) {
tcg_gen_shri_vec(vece, tmp, b, (4 << (vece - i))); tcg_gen_shri_vec(vece, tmp, b, (4 << (vece - i)));
tcg_gen_xor_vec(vece, b, tmp, b); tcg_gen_xor_vec(vece, b, tmp, b);