mirror of https://github.com/xemu-project/xemu.git
target/mips: Add field and R/W access to ITU control register ICR0
Add field and R/W access to ITU control register ICR0. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
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@ -55,9 +55,17 @@ typedef enum ITCView {
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ITCVIEW_EF_SYNC = 2,
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ITCVIEW_EF_TRY = 3,
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ITCVIEW_PV_SYNC = 4,
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ITCVIEW_PV_TRY = 5
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ITCVIEW_PV_TRY = 5,
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ITCVIEW_PV_ICR0 = 15,
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} ITCView;
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#define ITC_ICR0_CELL_NUM 16
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#define ITC_ICR0_BLK_GRAIN 8
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#define ITC_ICR0_BLK_GRAIN_MASK 0x7
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#define ITC_ICR0_ERR_AXI 2
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#define ITC_ICR0_ERR_PARITY 1
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#define ITC_ICR0_ERR_EXEC 0
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MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu)
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{
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return &itu->tag_io;
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@ -382,6 +390,9 @@ static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
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case ITCVIEW_PV_TRY:
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ret = view_pv_try_read(cell);
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break;
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case ITCVIEW_PV_ICR0:
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ret = s->icr0;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"itc_storage_read: Bad ITC View %d\n", (int)view);
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@ -417,6 +428,15 @@ static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data,
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case ITCVIEW_PV_TRY:
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view_pv_try_write(cell);
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break;
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case ITCVIEW_PV_ICR0:
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if (data & 0x7) {
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/* clear ERROR bits */
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s->icr0 &= ~(data & 0x7);
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}
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/* set BLK_GRAIN */
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s->icr0 &= ~0x700;
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s->icr0 |= data & 0x700;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"itc_storage_write: Bad ITC View %d\n", (int)view);
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@ -66,6 +66,10 @@ typedef struct MIPSITUState {
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/* ITC Configuration Tags */
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uint64_t ITCAddressMap[ITC_ADDRESSMAP_NUM];
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MemoryRegion tag_io;
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/* ITU Control Register */
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uint64_t icr0;
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} MIPSITUState;
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/* Get ITC Configuration Tag memory region. */
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