From e43692bce684b76480df66473a9b3bec7a7d312a Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Mon, 28 Aug 2023 13:26:45 +0200 Subject: [PATCH] target/tricore: Clarify special case for FTOUZ insn this is not something other ISAs do, so clarify it with a comment. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Message-ID: <20230828112651.522058-6-kbastian@mail.uni-paderborn.de> --- target/tricore/fpu_helper.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c index 3aefeb776e..d0c474c5f3 100644 --- a/target/tricore/fpu_helper.c +++ b/target/tricore/fpu_helper.c @@ -475,6 +475,11 @@ uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg) if (float32_is_any_nan(f_arg)) { result = 0; } + /* + * we need to check arg < 0.0 before rounding as TriCore needs to raise + * float_flag_invalid as well. For instance, when we have a negative + * exponent and sign, softfloat would only raise float_flat_inexact. + */ } else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) { flags = float_flag_invalid; result = 0;