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tcg/mips: Use tcg_use_softmmu 

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-10-01 11:49:03 -07:00
parent 10e1fd2784
commit e3a650cd9d
1 changed files with 113 additions and 118 deletions
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25
tcg/mips/tcg-target.c.inc
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@ -78,13 +78,11 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
#define TCG_TMP2 TCG_REG_T8
#define TCG_TMP3 TCG_REG_T7
#ifndef CONFIG_SOFTMMU
#define TCG_GUEST_BASE_REG TCG_REG_S7
#endif
#if TCG_TARGET_REG_BITS == 64
#define TCG_REG_TB TCG_REG_S6
#else
#define TCG_REG_TB (qemu_build_not_reached(), TCG_REG_ZERO)
#define TCG_REG_TB ({ qemu_build_not_reached(); TCG_REG_ZERO; })
#endif
/* check if we really need so many registers :P */
@ -1279,7 +1277,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
a_bits = h->aa.align;
a_mask = (1 << a_bits) - 1;
#ifdef CONFIG_SOFTMMU
if (tcg_use_softmmu) {
unsigned s_mask = (1 << s_bits) - 1;
int mem_index = get_mmuidx(oi);
int fast_off = tlb_mask_table_ofs(s, mem_index);
@ -1309,7 +1307,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
}
tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0);
/* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */
/* Add the tlb_table pointer, creating the CPUTLBEntry address. */
tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1);
if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) {
@ -1332,11 +1330,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
*/
tcg_out_movi(s, addr_type, TCG_TMP1, s->page_mask | a_mask);
if (a_mask < s_mask) {
if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) {
tcg_out_opc_imm(s, OPC_ADDIU, TCG_TMP2, addrlo, s_mask - a_mask);
} else {
tcg_out_opc_imm(s, OPC_DADDIU, TCG_TMP2, addrlo, s_mask - a_mask);
}
tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS == 32
|| addr_type == TCG_TYPE_I32
? OPC_ADDIU : OPC_DADDIU),
TCG_TMP2, addrlo, s_mask - a_mask);
tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2);
} else {
tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo);
@ -1366,7 +1363,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
/* delay slot */
base = TCG_TMP3;
tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addrlo);
#else
} else {
if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) {
ldst = new_ldst_label(s);
@ -1402,7 +1399,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
}
base = TCG_REG_A0;
}
#endif
}
h->base = base;
return ldst;
@ -2465,8 +2462,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)
TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
}
#ifndef CONFIG_SOFTMMU
if (guest_base != (int16_t)guest_base) {
if (!tcg_use_softmmu && guest_base != (int16_t)guest_base) {
/*
* The function call abi for n32 and n64 will have loaded $25 (t9)
* with the address of the prologue, so we can use that instead
@ -2479,7 +2475,6 @@ static void tcg_target_qemu_prologue(TCGContext *s)
TCG_TARGET_REG_BITS == 64 ? TCG_REG_T9 : 0);
tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
}
#endif
if (TCG_TARGET_REG_BITS == 64) {
tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]);