From e37fdc73811dd40ccf1409e1edb9f7403283dd87 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 12 Jul 2023 07:51:44 +0200 Subject: [PATCH] target/mips/mxu: Avoid overrun in gen_mxu_S32SLT() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Coverity reports a potential overrun (CID 1517769): Overrunning array "mxu_gpr" of 15 8-byte elements at element index 4294967295 (byte offset 34359738367) using index "XRb - 1U" (which evaluates to 4294967295). Use gen_load_mxu_gpr() to safely load MXU registers. Fixes: ff7936f009 ("target/mips/mxu: Add S32SLT ... insns") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20230712060806.82323-3-philmd@linaro.org> --- target/mips/tcg/mxu_translate.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c index b007948a73..520747a597 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -2434,8 +2434,12 @@ static void gen_mxu_S32SLT(DisasContext *ctx) tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0); } else { /* the most general case */ - tcg_gen_setcond_tl(TCG_COND_LT, mxu_gpr[XRa - 1], - mxu_gpr[XRb - 1], mxu_gpr[XRc - 1]); + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + + gen_load_mxu_gpr(t0, XRb); + gen_load_mxu_gpr(t1, XRc); + tcg_gen_setcond_tl(TCG_COND_LT, mxu_gpr[XRa - 1], t0, t1); } }