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target/sparc: Populate CPUClass.mmu_index 

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-01-29 11:01:52 +10:00
parent 9ba49d7222
commit e3547a7d07
2 changed files with 35 additions and 28 deletions
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29
target/sparc/cpu.c
View File

@ -718,6 +718,34 @@ static bool sparc_cpu_has_work(CPUState *cs)
cpu_interrupts_enabled(env);
}
int sparc_cpu_mmu_index(CPUState *cs, bool ifetch)
{
CPUSPARCState *env = cpu_env(cs);
#ifndef TARGET_SPARC64
if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
return MMU_PHYS_IDX;
} else {
return env->psrs;
}
#else
/* IMMU or DMMU disabled. */
if (ifetch
? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0
: (env->lsu & DMMU_E) == 0) {
return MMU_PHYS_IDX;
} else if (cpu_hypervisor_mode(env)) {
return MMU_PHYS_IDX;
} else if (env->tl > 0) {
return MMU_NUCLEUS_IDX;
} else if (cpu_supervisor_mode(env)) {
return MMU_KERNEL_IDX;
} else {
return MMU_USER_IDX;
}
#endif
}
static char *sparc_cpu_type_name(const char *cpu_model)
{
char *name = g_strdup_printf(SPARC_CPU_TYPE_NAME("%s"), cpu_model);
@ -906,6 +934,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = sparc_cpu_class_by_name;
cc->parse_features = sparc_cpu_parse_features;
cc->has_work = sparc_cpu_has_work;
cc->mmu_index = sparc_cpu_mmu_index;
cc->dump_state = sparc_cpu_dump_state;
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
cc->memory_rw_debug = sparc_cpu_memory_rw_debug;

34
target/sparc/cpu.h
View File

@ -708,34 +708,6 @@ static inline int cpu_supervisor_mode(CPUSPARCState *env1)
}
#endif
static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch)
{
#if defined(CONFIG_USER_ONLY)
return MMU_USER_IDX;
#elif !defined(TARGET_SPARC64)
if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
return MMU_PHYS_IDX;
} else {
return env->psrs;
}
#else
/* IMMU or DMMU disabled. */
if (ifetch
? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0
: (env->lsu & DMMU_E) == 0) {
return MMU_PHYS_IDX;
} else if (cpu_hypervisor_mode(env)) {
return MMU_PHYS_IDX;
} else if (env->tl > 0) {
return MMU_NUCLEUS_IDX;
} else if (cpu_supervisor_mode(env)) {
return MMU_KERNEL_IDX;
} else {
return MMU_USER_IDX;
}
#endif
}
static inline int cpu_interrupts_enabled(CPUSPARCState *env1)
{
#if !defined (TARGET_SPARC64)
@ -777,6 +749,12 @@ trap_state* cpu_tsptr(CPUSPARCState* env);
#define TB_FLAG_HYPER (1 << 7)
#define TB_FLAG_ASI_SHIFT 24
int sparc_cpu_mmu_index(CPUState *cs, bool ifetch);
static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch)
{
return sparc_cpu_mmu_index(env_cpu(env), ifetch);
}
static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *pflags)
{