mirror of https://github.com/xemu-project/xemu.git
PowerPC: IDE DB-DMA support
This patches allows powermac IDE interface to use DB-DMA. This implementation uses only synchronous I/O. Signed-off-by: Laurent Vivier <Laurent@lvivier.info> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6489 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32
parent
28ce5ce63b
commit
e3007e6677
170
hw/ide.c
170
hw/ide.c
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@ -31,6 +31,7 @@
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#include "qemu-timer.h"
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#include "sysemu.h"
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#include "ppc_mac.h"
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#include "mac_dbdma.h"
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#include "sh.h"
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/* debug IDE devices */
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@ -437,6 +438,8 @@ typedef struct IDEState {
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uint32_t mdata_size;
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uint8_t *mdata_storage;
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int media_changed;
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/* for pmac */
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int is_read;
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} IDEState;
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/* XXX: DVDs that could fit on a CD will be reported as a CD */
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@ -1094,6 +1097,7 @@ static void ide_sector_read_dma(IDEState *s)
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s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
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s->io_buffer_index = 0;
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s->io_buffer_size = 0;
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s->is_read = 1;
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ide_dma_start(s, ide_read_dma_cb);
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}
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@ -1222,6 +1226,7 @@ static void ide_sector_write_dma(IDEState *s)
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s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
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s->io_buffer_index = 0;
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s->io_buffer_size = 0;
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s->is_read = 0;
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ide_dma_start(s, ide_write_dma_cb);
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}
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@ -3473,21 +3478,130 @@ void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
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register_savevm("ide", 0, 2, pci_ide_save, pci_ide_load, d);
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}
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#if defined(TARGET_PPC)
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/***********************************************************/
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/* MacIO based PowerPC IDE */
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typedef struct MACIOIDEState {
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IDEState ide_if[2];
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void *dbdma;
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int stream_index;
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} MACIOIDEState;
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static int pmac_atapi_read(DBDMA_transfer *info, DBDMA_transfer_cb cb)
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{
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MACIOIDEState *m = info->opaque;
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IDEState *s = m->ide_if->cur_drive;
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int ret;
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if (s->lba == -1)
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return 0;
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info->buf_pos = 0;
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while (info->buf_pos < info->len && s->packet_transfer_size > 0) {
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ret = cd_read_sector(s->bs, s->lba, s->io_buffer, s->cd_sector_size);
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if (ret < 0) {
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ide_transfer_stop(s);
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ide_atapi_io_error(s, ret);
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return info->buf_pos;
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}
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info->buf = s->io_buffer + m->stream_index;
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info->buf_len = s->cd_sector_size;
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if (info->buf_pos + info->buf_len > info->len)
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info->buf_len = info->len - info->buf_pos;
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cb(info);
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/* db-dma can ask for 512 bytes whereas block size is 2048... */
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m->stream_index += info->buf_len;
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s->lba += m->stream_index / s->cd_sector_size;
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m->stream_index %= s->cd_sector_size;
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info->buf_pos += info->buf_len;
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s->packet_transfer_size -= info->buf_len;
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}
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if (s->packet_transfer_size <= 0) {
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s->status = READY_STAT | SEEK_STAT;
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s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO
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| ATAPI_INT_REASON_CD;
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ide_set_irq(s);
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}
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return info->buf_pos;
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}
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static int pmac_ide_transfer(DBDMA_transfer *info,
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DBDMA_transfer_cb cb)
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{
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MACIOIDEState *m = info->opaque;
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IDEState *s = m->ide_if->cur_drive;
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int64_t sector_num;
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int ret, n;
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if (s->is_cdrom)
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return pmac_atapi_read(info, cb);
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info->buf = s->io_buffer;
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info->buf_pos = 0;
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while (info->buf_pos < info->len && s->nsector > 0) {
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sector_num = ide_get_sector(s);
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n = s->nsector;
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if (n > IDE_DMA_BUF_SECTORS)
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n = IDE_DMA_BUF_SECTORS;
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info->buf_len = n << 9;
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if (info->buf_pos + info->buf_len > info->len)
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info->buf_len = info->len - info->buf_pos;
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n = info->buf_len >> 9;
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if (s->is_read) {
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ret = bdrv_read(s->bs, sector_num, s->io_buffer, n);
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if (ret == 0)
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cb(info);
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} else {
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cb(info);
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ret = bdrv_write(s->bs, sector_num, s->io_buffer, n);
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}
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if (ret != 0) {
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ide_rw_error(s);
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return info->buf_pos;
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}
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info->buf_pos += n << 9;
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ide_set_sector(s, sector_num + n);
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s->nsector -= n;
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}
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if (s->nsector <= 0) {
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s->status = READY_STAT | SEEK_STAT;
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ide_set_irq(s);
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}
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return info->buf_pos;
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}
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/* PowerMac IDE memory IO */
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static void pmac_ide_writeb (void *opaque,
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target_phys_addr_t addr, uint32_t val)
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{
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MACIOIDEState *d = opaque;
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addr = (addr & 0xFFF) >> 4;
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switch (addr) {
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case 1 ... 7:
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ide_ioport_write(opaque, addr, val);
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ide_ioport_write(d->ide_if, addr, val);
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break;
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case 8:
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case 22:
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ide_cmd_write(opaque, 0, val);
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ide_cmd_write(d->ide_if, 0, val);
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break;
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default:
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break;
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@ -3497,15 +3611,16 @@ static void pmac_ide_writeb (void *opaque,
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static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
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{
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uint8_t retval;
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MACIOIDEState *d = opaque;
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addr = (addr & 0xFFF) >> 4;
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switch (addr) {
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case 1 ... 7:
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retval = ide_ioport_read(opaque, addr);
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retval = ide_ioport_read(d->ide_if, addr);
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break;
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case 8:
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case 22:
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retval = ide_status_read(opaque, 0);
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retval = ide_status_read(d->ide_if, 0);
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break;
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default:
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retval = 0xFF;
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@ -3517,22 +3632,25 @@ static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
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static void pmac_ide_writew (void *opaque,
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target_phys_addr_t addr, uint32_t val)
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{
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MACIOIDEState *d = opaque;
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addr = (addr & 0xFFF) >> 4;
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap16(val);
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#endif
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if (addr == 0) {
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ide_data_writew(opaque, 0, val);
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ide_data_writew(d->ide_if, 0, val);
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}
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}
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static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
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{
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uint16_t retval;
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MACIOIDEState *d = opaque;
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addr = (addr & 0xFFF) >> 4;
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if (addr == 0) {
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retval = ide_data_readw(opaque, 0);
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retval = ide_data_readw(d->ide_if, 0);
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} else {
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retval = 0xFFFF;
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}
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@ -3545,22 +3663,25 @@ static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
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static void pmac_ide_writel (void *opaque,
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target_phys_addr_t addr, uint32_t val)
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{
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MACIOIDEState *d = opaque;
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addr = (addr & 0xFFF) >> 4;
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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if (addr == 0) {
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ide_data_writel(opaque, 0, val);
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ide_data_writel(d->ide_if, 0, val);
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}
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}
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static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
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{
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uint32_t retval;
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MACIOIDEState *d = opaque;
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addr = (addr & 0xFFF) >> 4;
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if (addr == 0) {
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retval = ide_data_readl(opaque, 0);
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retval = ide_data_readl(d->ide_if, 0);
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} else {
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retval = 0xFFFFFFFF;
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}
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@ -3584,7 +3705,8 @@ static CPUReadMemoryFunc *pmac_ide_read[] = {
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static void pmac_ide_save(QEMUFile *f, void *opaque)
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{
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IDEState *s = (IDEState *)opaque;
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MACIOIDEState *d = opaque;
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IDEState *s = d->ide_if;
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uint8_t drive1_selected;
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unsigned int i;
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@ -3601,7 +3723,8 @@ static void pmac_ide_save(QEMUFile *f, void *opaque)
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static int pmac_ide_load(QEMUFile *f, void *opaque, int version_id)
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{
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IDEState *s = (IDEState *)opaque;
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MACIOIDEState *d = opaque;
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IDEState *s = d->ide_if;
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uint8_t drive1_selected;
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unsigned int i;
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@ -3622,7 +3745,8 @@ static int pmac_ide_load(QEMUFile *f, void *opaque, int version_id)
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static void pmac_ide_reset(void *opaque)
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{
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IDEState *s = (IDEState *)opaque;
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MACIOIDEState *d = opaque;
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IDEState *s = d->ide_if;
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ide_reset(&s[0]);
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ide_reset(&s[1]);
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@ -3631,21 +3755,29 @@ static void pmac_ide_reset(void *opaque)
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/* hd_table must contain 4 block drivers */
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/* PowerMac uses memory mapped registers, not I/O. Return the memory
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I/O index to access the ide. */
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int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq)
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int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq,
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void *dbdma, int channel, qemu_irq dma_irq)
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{
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IDEState *ide_if;
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MACIOIDEState *d;
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int pmac_ide_memory;
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ide_if = qemu_mallocz(sizeof(IDEState) * 2);
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ide_init2(&ide_if[0], hd_table[0], hd_table[1], irq);
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d = qemu_mallocz(sizeof(MACIOIDEState));
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ide_init2(d->ide_if, hd_table[0], hd_table[1], irq);
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if (dbdma) {
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d->dbdma = dbdma;
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DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, d);
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}
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pmac_ide_memory = cpu_register_io_memory(0, pmac_ide_read,
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pmac_ide_write, &ide_if[0]);
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register_savevm("ide", 0, 1, pmac_ide_save, pmac_ide_load, &ide_if[0]);
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qemu_register_reset(pmac_ide_reset, &ide_if[0]);
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pmac_ide_reset(&ide_if[0]);
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pmac_ide_write, d);
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register_savevm("ide", 0, 1, pmac_ide_save, pmac_ide_load, d);
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qemu_register_reset(pmac_ide_reset, d);
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pmac_ide_reset(d);
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return pmac_ide_memory;
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}
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#endif /* TARGET_PPC */
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/***********************************************************/
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/* MMIO based ide port
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@ -284,8 +284,8 @@ static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size,
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}
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dbdma = DBDMA_init(&dbdma_mem_index);
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#if 1
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ide_mem_index[0] = pmac_ide_init(&hd[0], pic[0x13]);
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ide_mem_index[1] = pmac_ide_init(&hd[2], pic[0x14]);
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ide_mem_index[0] = pmac_ide_init(&hd[0], pic[0x13], dbdma, 0x14, pic[0x01]);
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ide_mem_index[1] = pmac_ide_init(&hd[2], pic[0x14], dbdma, 0x16, pic[0x02]);
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#else
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pci_cmd646_ide_init(pci_bus, &hd[0], 0);
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#endif
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@ -48,7 +48,8 @@ void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index,
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int nb_ide, int *ide_mem_index, int escc_mem_index);
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/* NewWorld PowerMac IDE */
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int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq);
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int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq,
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void *dbdma, int channel, qemu_irq dma_irq);
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/* Heathrow PIC */
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qemu_irq *heathrow_pic_init(int *pmem_index,
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@ -349,7 +349,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
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dbdma = DBDMA_init(&dbdma_mem_index);
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ide_mem_index[0] = -1;
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ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D]);
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ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D], dbdma, 0x16, pic[0x02]);
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/* cuda also initialize ADB */
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cuda_init(&cuda_mem_index, pic[0x12]);
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