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tests/qtest: Add xscom tests for powernv10 machine
Add basic chip and core xscom tests for powernv10 machine, equivalent to tests for powernv8 and 9. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20230706053923.115003-3-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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tests/qtest
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@ -15,6 +15,7 @@ typedef enum PnvChipType {
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PNV_CHIP_POWER8, /* AKA Venice */
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PNV_CHIP_POWER8NVL, /* AKA Naples */
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PNV_CHIP_POWER9, /* AKA Nimbus */
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PNV_CHIP_POWER10,
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} PnvChipType;
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typedef struct PnvChip {
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@ -46,13 +47,22 @@ static const PnvChip pnv_chips[] = {
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.cfam_id = 0x220d104900008000ull,
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.first_core = 0x0,
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},
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{
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.chip_type = PNV_CHIP_POWER10,
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.cpu_model = "POWER10",
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.xscom_base = 0x000603fc00000000ull,
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.cfam_id = 0x120da04900008000ull,
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.first_core = 0x0,
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},
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};
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static uint64_t pnv_xscom_addr(const PnvChip *chip, uint32_t pcba)
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{
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uint64_t addr = chip->xscom_base;
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if (chip->chip_type == PNV_CHIP_POWER9) {
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if (chip->chip_type == PNV_CHIP_POWER10) {
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addr |= ((uint64_t) pcba << 3);
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} else if (chip->chip_type == PNV_CHIP_POWER9) {
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addr |= ((uint64_t) pcba << 3);
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} else {
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addr |= (((uint64_t) pcba << 4) & ~0xffull) |
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@ -82,6 +92,8 @@ static void test_cfam_id(const void *data)
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if (chip->chip_type == PNV_CHIP_POWER9) {
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machine = "powernv9";
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} else if (chip->chip_type == PNV_CHIP_POWER10) {
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machine = "powernv10";
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}
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qts = qtest_initf("-M %s -accel tcg -cpu %s",
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@ -96,23 +108,36 @@ static void test_cfam_id(const void *data)
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(PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24))
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#define PNV_XSCOM_P9_EC_BASE(core) \
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((uint64_t)(((core) & 0x1F) + 0x20) << 24)
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#define PNV_XSCOM_P10_EC_BASE(core) \
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((uint64_t)((((core) & ~0x3) + 0x20) << 24) + 0x20000 + \
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(0x1000 << (3 - (core & 0x3))))
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#define PNV_XSCOM_EX_DTS_RESULT0 0x50000
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static void test_xscom_core(QTestState *qts, const PnvChip *chip)
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{
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uint32_t first_core_dts0 = PNV_XSCOM_EX_DTS_RESULT0;
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uint64_t dts0;
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if (chip->chip_type == PNV_CHIP_POWER10) {
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uint32_t first_core_thread_state =
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PNV_XSCOM_P10_EC_BASE(chip->first_core) + 0x412;
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uint64_t thread_state;
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if (chip->chip_type != PNV_CHIP_POWER9) {
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first_core_dts0 |= PNV_XSCOM_EX_BASE(chip->first_core);
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thread_state = pnv_xscom_read(qts, chip, first_core_thread_state);
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g_assert_cmphex(thread_state, ==, 0);
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} else {
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first_core_dts0 |= PNV_XSCOM_P9_EC_BASE(chip->first_core);
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uint32_t first_core_dts0 = PNV_XSCOM_EX_DTS_RESULT0;
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uint64_t dts0;
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if (chip->chip_type == PNV_CHIP_POWER9) {
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first_core_dts0 |= PNV_XSCOM_P9_EC_BASE(chip->first_core);
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} else { /* POWER8 */
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first_core_dts0 |= PNV_XSCOM_EX_BASE(chip->first_core);
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}
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dts0 = pnv_xscom_read(qts, chip, first_core_dts0);
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g_assert_cmphex(dts0, ==, 0x26f024f023f0000ull);
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}
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dts0 = pnv_xscom_read(qts, chip, first_core_dts0);
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g_assert_cmphex(dts0, ==, 0x26f024f023f0000ull);
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}
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static void test_core(const void *data)
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@ -123,6 +148,8 @@ static void test_core(const void *data)
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if (chip->chip_type == PNV_CHIP_POWER9) {
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machine = "powernv9";
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} else if (chip->chip_type == PNV_CHIP_POWER10) {
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machine = "powernv10";
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}
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qts = qtest_initf("-M %s -accel tcg -cpu %s",
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