mirror of https://github.com/xemu-project/xemu.git
vga: a collection of ati fixes/improvements.
-----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABAgAGBQJdXkykAAoJEEy22O7T6HE4ov4P/2c6oOaDWoD1nPHpVCh8ygQi XttAd46/WObe9UG2mqA5Ds91e5cbqilgvAXCfDO9OsmoceEdLwrsbrJf+98Em92t Fn+6v8ywGo6YUdvqzvYFBEMQjtd8lVFEnUf3DXrf4OkMkuhJ3FVwTvhrDXr+6MJZ 4nDj2cSltXvjU9Z+e/7T0chGkqOPkPTg84wMhYyjAFzjOdxSmkeOe5RTRHgaMD/t 96oQi/tOdk60g/DxZSGA1Hqm2kNbzpi5ZFCuvFPum3rJRpErt/BcxCPNYAOAbbq0 bjcF1gmAW2RVDtqJyQHiYhm6AAc0FPuFh4otJIgG9HXSevOOq3ijQRZP7xGVhpRF Xy2TuWxLuxz298W59/pYcJWPiNpGBCgWeejB10B7KwTegpe51boDLzmqFTN1TOVa sgKPr6QUu0BJHwgCxI/Jm79TkBHO54gVXGWE1SNUCxjMpR4VxcvKUM8pzE7pRT7B Q6fdqKG+WTeEsWv7aa9kHTWAf9lbsb2zL+9EOgD/tz5s0uUuU/HBIkk0JFC+h+7r eZxD49EtOSjteikkE4qqP0iPgH+DOCEASJRFjEe9JoilXWxmhaJw3e4x3V8ey1AK Xrro5VOmC+czjCi/gDnx3REB7kwkwEJnBLCGSgCruSPYgEvCA4BSMVtCwNhOEUx1 lU4IqcpArtrw0B+ci3c2 =xT8w -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/kraxel/tags/vga-20190822-pull-request' into staging vga: a collection of ati fixes/improvements. # gpg: Signature made Thu 22 Aug 2019 09:04:52 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/vga-20190822-pull-request: ati-vga: Implement dummy VBlank IRQ ati-vga: Add limited support for big endian frame buffer aperture ati-vga: Attempt to handle CRTC offset not exact multiple of stride ati-vga: Fix hardware cursor image offset ati-vga: Fix cursor color with guest_hwcursor=true ati-vga: Fix GPIO_MONID register write ati-vga: Add some register definitions for debugging ati-vga: Add registers for getting apertures Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
e1391340c7
112
hw/display/ati.c
112
hw/display/ati.c
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@ -50,6 +50,7 @@ static void ati_vga_switch_mode(ATIVGAState *s)
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s->mode = EXT_MODE;
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if (s->regs.crtc_gen_cntl & CRTC2_EN) {
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/* CRT controller enabled, use CRTC values */
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/* FIXME Should these be the same as VGA CRTC regs? */
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uint32_t offs = s->regs.crtc_offset & 0x07ffffff;
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int stride = (s->regs.crtc_pitch & 0x7ff) * 8;
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int bpp = 0;
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@ -89,7 +90,9 @@ static void ati_vga_switch_mode(ATIVGAState *s)
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DPRINTF("Switching to %dx%d %d %d @ %x\n", h, v, stride, bpp, offs);
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vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE);
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vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_DISABLED);
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s->vga.big_endian_fb = false;
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s->vga.big_endian_fb = (s->regs.config_cntl & APER_0_ENDIAN ||
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s->regs.config_cntl & APER_1_ENDIAN ?
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true : false);
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/* reset VBE regs then set up mode */
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s->vga.vbe_regs[VBE_DISPI_INDEX_XRES] = h;
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s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] = v;
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@ -101,16 +104,23 @@ static void ati_vga_switch_mode(ATIVGAState *s)
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(s->regs.dac_cntl & DAC_8BIT_EN ? VBE_DISPI_8BIT_DAC : 0));
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/* now set offset and stride after enable as that resets these */
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if (stride) {
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int bypp = DIV_ROUND_UP(bpp, BITS_PER_BYTE);
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vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_VIRT_WIDTH);
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vbe_ioport_write_data(&s->vga, 0, stride);
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if (offs % stride == 0) {
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vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_Y_OFFSET);
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vbe_ioport_write_data(&s->vga, 0, offs / stride);
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} else {
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/* FIXME what to do with this? */
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error_report("VGA offset is not multiple of pitch, "
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"expect bad picture");
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stride *= bypp;
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if (offs % stride) {
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DPRINTF("CRTC offset is not multiple of pitch\n");
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vbe_ioport_write_index(&s->vga, 0,
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VBE_DISPI_INDEX_X_OFFSET);
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vbe_ioport_write_data(&s->vga, 0, offs % stride / bypp);
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}
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vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_Y_OFFSET);
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vbe_ioport_write_data(&s->vga, 0, offs / stride);
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DPRINTF("VBE offset (%d,%d), vbe_start_addr=%x\n",
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s->vga.vbe_regs[VBE_DISPI_INDEX_X_OFFSET],
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s->vga.vbe_regs[VBE_DISPI_INDEX_Y_OFFSET],
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s->vga.vbe_start_addr);
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}
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}
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} else {
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@ -132,9 +142,8 @@ static void ati_cursor_define(ATIVGAState *s)
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return; /* Do not update cursor if locked or rendered by guest */
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}
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/* FIXME handle cur_hv_offs correctly */
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src = s->vga.vram_ptr + (s->regs.crtc_offset & 0x07ffffff) +
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s->regs.cur_offset - (s->regs.cur_hv_offs >> 16) -
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(s->regs.cur_hv_offs & 0xffff) * 16;
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src = s->vga.vram_ptr + s->regs.cur_offset -
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(s->regs.cur_hv_offs >> 16) - (s->regs.cur_hv_offs & 0xffff) * 16;
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for (i = 0; i < 64; i++) {
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for (j = 0; j < 8; j++, idx++) {
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data[idx] = src[i * 16 + j];
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@ -190,8 +199,7 @@ static void ati_cursor_draw_line(VGACommonState *vga, uint8_t *d, int scr_y)
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return;
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}
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/* FIXME handle cur_hv_offs correctly */
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src = s->vga.vram_ptr + (s->regs.crtc_offset & 0x07ffffff) +
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s->cursor_offset + (scr_y - vga->hw_cursor_y) * 16;
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src = s->vga.vram_ptr + s->cursor_offset + (scr_y - vga->hw_cursor_y) * 16;
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dp = &dp[vga->hw_cursor_x];
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h = ((s->regs.crtc_h_total_disp >> 16) + 1) * 8;
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for (i = 0; i < 8; i++) {
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@ -207,7 +215,7 @@ static void ati_cursor_draw_line(VGACommonState *vga, uint8_t *d, int scr_y)
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}
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} else {
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color = (xbits & BIT(7) ? s->regs.cur_color1 :
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s->regs.cur_color0) << 8 | 0xff;
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s->regs.cur_color0) | 0xff000000;
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}
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if (vga->hw_cursor_x + i * 8 + j >= h) {
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return; /* end of screen, don't span to next line */
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@ -235,6 +243,21 @@ static uint64_t ati_i2c(bitbang_i2c_interface *i2c, uint64_t data, int base)
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return data;
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}
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static void ati_vga_update_irq(ATIVGAState *s)
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{
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pci_set_irq(&s->dev, !!(s->regs.gen_int_status & s->regs.gen_int_cntl));
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}
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static void ati_vga_vblank_irq(void *opaque)
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{
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ATIVGAState *s = opaque;
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timer_mod(&s->vblank_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
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NANOSECONDS_PER_SECOND / 60);
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s->regs.gen_int_status |= CRTC_VBLANK_INT;
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ati_vga_update_irq(s);
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}
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static inline uint64_t ati_reg_read_offs(uint32_t reg, int offs,
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unsigned int size)
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{
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@ -275,6 +298,12 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr, unsigned int size)
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addr - (BIOS_0_SCRATCH + i * 4), size);
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break;
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}
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case GEN_INT_CNTL:
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val = s->regs.gen_int_cntl;
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break;
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case GEN_INT_STATUS:
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val = s->regs.gen_int_status;
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break;
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case CRTC_GEN_CNTL ... CRTC_GEN_CNTL + 3:
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val = ati_reg_read_offs(s->regs.crtc_gen_cntl,
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addr - CRTC_GEN_CNTL, size);
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@ -304,9 +333,27 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr, unsigned int size)
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case PALETTE_DATA:
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val = vga_ioport_read(&s->vga, VGA_PEL_D);
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break;
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case CNFG_CNTL:
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val = s->regs.config_cntl;
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break;
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case CNFG_MEMSIZE:
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val = s->vga.vram_size;
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break;
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case CONFIG_APER_0_BASE:
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case CONFIG_APER_1_BASE:
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val = pci_default_read_config(&s->dev,
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PCI_BASE_ADDRESS_0, size) & 0xfffffff0;
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break;
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case CONFIG_APER_SIZE:
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val = s->vga.vram_size;
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break;
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case CONFIG_REG_1_BASE:
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val = pci_default_read_config(&s->dev,
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PCI_BASE_ADDRESS_2, size) & 0xfffffff0;
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break;
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case CONFIG_REG_APER_SIZE:
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val = memory_region_size(&s->mm);
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break;
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case MC_STATUS:
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val = 5;
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break;
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@ -486,6 +533,21 @@ static void ati_mm_write(void *opaque, hwaddr addr,
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addr - (BIOS_0_SCRATCH + i * 4), data, size);
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break;
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}
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case GEN_INT_CNTL:
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s->regs.gen_int_cntl = data;
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if (data & CRTC_VBLANK_INT) {
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ati_vga_vblank_irq(s);
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} else {
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timer_del(&s->vblank_timer);
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ati_vga_update_irq(s);
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}
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break;
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case GEN_INT_STATUS:
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data &= (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF ?
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0x000f040fUL : 0xfc080effUL);
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s->regs.gen_int_status &= ~data;
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ati_vga_update_irq(s);
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break;
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case CRTC_GEN_CNTL ... CRTC_GEN_CNTL + 3:
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{
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uint32_t val = s->regs.crtc_gen_cntl;
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@ -549,12 +611,15 @@ static void ati_mm_write(void *opaque, hwaddr addr,
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addr - GPIO_MONID, data, size);
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/*
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* Rage128p accesses DDC used to get EDID via these bits.
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* Only touch i2c when write overlaps 3rd byte because some
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* drivers access this reg via multiple partial writes and
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* without this spurious bits would be sent.
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* Because some drivers access this via multiple byte writes
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* we have to be careful when we send bits to avoid spurious
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* changes in bitbang_i2c state. So only do it when mask is set
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* and either the enable bits are changed or output bits changed
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* while enabled.
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*/
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if ((s->regs.gpio_monid & BIT(25)) &&
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addr <= GPIO_MONID + 2 && addr + size > GPIO_MONID + 2) {
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((addr <= GPIO_MONID + 2 && addr + size > GPIO_MONID + 2) ||
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(addr == GPIO_MONID && (s->regs.gpio_monid & 0x60000)))) {
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s->regs.gpio_monid = ati_i2c(&s->bbi2c, s->regs.gpio_monid, 1);
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}
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}
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@ -580,6 +645,9 @@ static void ati_mm_write(void *opaque, hwaddr addr,
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data >>= 8;
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vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff);
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break;
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case CNFG_CNTL:
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s->regs.config_cntl = data;
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break;
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case CRTC_H_TOTAL_DISP:
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s->regs.crtc_h_total_disp = data & 0x07ff07ff;
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break;
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@ -870,12 +938,19 @@ static void ati_vga_realize(PCIDevice *dev, Error **errp)
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pci_register_bar(dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &vga->vram);
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pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
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pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mm);
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/* most interrupts are not yet emulated but MacOS needs at least VBlank */
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dev->config[PCI_INTERRUPT_PIN] = 1;
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timer_init_ns(&s->vblank_timer, QEMU_CLOCK_VIRTUAL, ati_vga_vblank_irq, s);
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}
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static void ati_vga_reset(DeviceState *dev)
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{
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ATIVGAState *s = ATI_VGA(dev);
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timer_del(&s->vblank_timer);
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ati_vga_update_irq(s);
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/* reset vga */
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vga_common_reset(&s->vga);
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s->mode = VGA_MODE;
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@ -885,6 +960,7 @@ static void ati_vga_exit(PCIDevice *dev)
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{
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ATIVGAState *s = ATI_VGA(dev);
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timer_del(&s->vblank_timer);
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graphic_console_close(s->vga.con);
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}
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@ -16,6 +16,7 @@ static struct ati_regdesc ati_reg_names[] = {
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{"BUS_CNTL", 0x0030},
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{"BUS_CNTL1", 0x0034},
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{"GEN_INT_CNTL", 0x0040},
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{"GEN_INT_STATUS", 0x0044},
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{"CRTC_GEN_CNTL", 0x0050},
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{"CRTC_EXT_CNTL", 0x0054},
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{"DAC_CNTL", 0x0058},
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@ -23,11 +24,20 @@ static struct ati_regdesc ati_reg_names[] = {
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{"GPIO_DVI_DDC", 0x0064},
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{"GPIO_MONID", 0x0068},
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{"I2C_CNTL_1", 0x0094},
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{"AMCGPIO_MASK_MIR", 0x009c},
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{"AMCGPIO_A_MIR", 0x00a0},
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{"AMCGPIO_Y_MIR", 0x00a4},
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{"AMCGPIO_EN_MIR", 0x00a8},
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{"PALETTE_INDEX", 0x00b0},
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{"PALETTE_DATA", 0x00b4},
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{"CNFG_CNTL", 0x00e0},
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{"GEN_RESET_CNTL", 0x00f0},
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{"CNFG_MEMSIZE", 0x00f8},
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{"CONFIG_APER_0_BASE", 0x0100},
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{"CONFIG_APER_1_BASE", 0x0104},
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{"CONFIG_APER_SIZE", 0x0108},
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{"CONFIG_REG_1_BASE", 0x010c},
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{"CONFIG_REG_APER_SIZE", 0x0110},
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{"MEM_CNTL", 0x0140},
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{"MC_FB_LOCATION", 0x0148},
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{"MC_AGP_LOCATION", 0x014C},
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|
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@ -9,6 +9,7 @@
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#ifndef ATI_INT_H
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#define ATI_INT_H
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#include "qemu/timer.h"
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#include "hw/pci/pci.h"
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#include "hw/i2c/bitbang_i2c.h"
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#include "vga_int.h"
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@ -33,12 +34,15 @@
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typedef struct ATIVGARegs {
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uint32_t mm_index;
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uint32_t bios_scratch[8];
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uint32_t gen_int_cntl;
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uint32_t gen_int_status;
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uint32_t crtc_gen_cntl;
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uint32_t crtc_ext_cntl;
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uint32_t dac_cntl;
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uint32_t gpio_vga_ddc;
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uint32_t gpio_dvi_ddc;
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uint32_t gpio_monid;
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uint32_t config_cntl;
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uint32_t crtc_h_total_disp;
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uint32_t crtc_h_sync_strt_wid;
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uint32_t crtc_v_total_disp;
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|
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@ -88,6 +92,7 @@ typedef struct ATIVGAState {
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uint16_t cursor_size;
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uint32_t cursor_offset;
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QEMUCursor *cursor;
|
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QEMUTimer vblank_timer;
|
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bitbang_i2c_interface bbi2c;
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MemoryRegion io;
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MemoryRegion mm;
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|
|
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|
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@ -34,6 +34,7 @@
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#define BUS_CNTL 0x0030
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#define BUS_CNTL1 0x0034
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#define GEN_INT_CNTL 0x0040
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#define GEN_INT_STATUS 0x0044
|
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#define CRTC_GEN_CNTL 0x0050
|
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#define CRTC_EXT_CNTL 0x0054
|
||||
#define DAC_CNTL 0x0058
|
||||
|
|
@ -41,11 +42,20 @@
|
|||
#define GPIO_DVI_DDC 0x0064
|
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#define GPIO_MONID 0x0068
|
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#define I2C_CNTL_1 0x0094
|
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#define AMCGPIO_MASK_MIR 0x009c
|
||||
#define AMCGPIO_A_MIR 0x00a0
|
||||
#define AMCGPIO_Y_MIR 0x00a4
|
||||
#define AMCGPIO_EN_MIR 0x00a8
|
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#define PALETTE_INDEX 0x00b0
|
||||
#define PALETTE_DATA 0x00b4
|
||||
#define CNFG_CNTL 0x00e0
|
||||
#define GEN_RESET_CNTL 0x00f0
|
||||
#define CNFG_MEMSIZE 0x00f8
|
||||
#define CONFIG_APER_0_BASE 0x0100
|
||||
#define CONFIG_APER_1_BASE 0x0104
|
||||
#define CONFIG_APER_SIZE 0x0108
|
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#define CONFIG_REG_1_BASE 0x010c
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||||
#define CONFIG_REG_APER_SIZE 0x0110
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||||
#define MEM_CNTL 0x0140
|
||||
#define MC_FB_LOCATION 0x0148
|
||||
#define MC_AGP_LOCATION 0x014C
|
||||
|
|
@ -307,7 +317,14 @@
|
|||
#define XPLL_FB_DIV_MASK 0x0000FF00
|
||||
#define X_MPLL_REF_DIV_MASK 0x000000FF
|
||||
|
||||
/* GEN_INT_CNTL) */
|
||||
#define CRTC_VBLANK_INT 0x00000001
|
||||
#define CRTC_VLINE_INT 0x00000002
|
||||
#define CRTC_VSYNC_INT 0x00000004
|
||||
|
||||
/* Config control values (CONFIG_CNTL) */
|
||||
#define APER_0_ENDIAN 0x00000003
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||||
#define APER_1_ENDIAN 0x0000000c
|
||||
#define CFG_VGA_IO_DIS 0x00000400
|
||||
|
||||
/* CRTC control values (CRTC_GEN_CNTL) */
|
||||
|
|
|
|||
Loading…
Reference in New Issue