From 59b1a90b0b5dc6b368364e9e1d40184eb4506c39 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Sat, 14 Apr 2018 18:06:34 +0200 Subject: [PATCH 1/5] target-microblaze: Respect MSR.PVR as read-only Respect MSR.PVR as read-only. We were wrongly overwriting the PVR bit. Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 7628b0e25b..f739751930 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -424,7 +424,7 @@ static inline void msr_write(DisasContext *dc, TCGv v) /* PVR bit is not writable. */ tcg_gen_andi_tl(t, v, ~MSR_PVR); tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR); - tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], v); + tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t); tcg_temp_free(t); } From 5153bb897a3d41d52c5b7187e9e40d5c26b04d57 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Sat, 14 Apr 2018 18:58:56 +0200 Subject: [PATCH 2/5] target-microblaze: Fix trap checks for FPU insns Fix trap checks for FPU insns when extended FPU insns are enabled. Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index f739751930..ec12fed49d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1412,7 +1412,7 @@ static void dec_fpu(DisasContext *dc) if ((dc->tb_flags & MSR_EE_FLAG) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && (dc->cpu->cfg.use_fpu != 1)) { + && !dc->cpu->cfg.use_fpu) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; From df1e528aad265a5c6ad7c84ef2861a5e4b2913bf Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Fri, 13 Apr 2018 20:45:14 +0200 Subject: [PATCH 3/5] target-microblaze: Don't clobber the IMM reg for ld/st reversed Do not clobber the IMM register on reversed load/stores. Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index ec12fed49d..100883e2cc 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -952,7 +952,6 @@ static void dec_load(DisasContext *dc) tcg_gen_sub_tl(low, tcg_const_tl(3), low); tcg_gen_andi_tl(t, t, ~3); tcg_gen_or_tl(t, t, low); - tcg_gen_mov_tl(env_imm, t); tcg_temp_free(low); break; } @@ -1104,7 +1103,6 @@ static void dec_store(DisasContext *dc) tcg_gen_sub_tl(low, tcg_const_tl(3), low); tcg_gen_andi_tl(t, t, ~3); tcg_gen_or_tl(t, t, low); - tcg_gen_mov_tl(env_imm, t); tcg_temp_free(low); break; } From bd9e66086b93a0a908a70a2679819d2d080d87b4 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Sun, 15 Apr 2018 23:05:22 +0200 Subject: [PATCH 4/5] target-microblaze: mmu: Make TLBSX write-only Make TLBSX write-only and guest-error log reads from it. Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/mmu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index a0f06758f8..8391811900 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -182,7 +182,7 @@ done: uint32_t mmu_read(CPUMBState *env, uint32_t rn) { unsigned int i; - uint32_t r; + uint32_t r = 0; if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) { qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n"); @@ -211,6 +211,9 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn) } r = env->mmu.regs[rn]; break; + case MMU_R_TLBSX: + qemu_log_mask(LOG_GUEST_ERROR, "TLBSX is write-only.\n"); + break; default: r = env->mmu.regs[rn]; break; From fce6a8eceb07e27f0cdea87427f4e560dfa0b1c8 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Sun, 15 Apr 2018 23:21:06 +0200 Subject: [PATCH 5/5] target-microblaze: mmu: Make the TLBX MISS bit read-only Make the TLBX MISS bit read-only. Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/mmu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 8391811900..9d5e6aa8a5 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -273,6 +273,10 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v) env->mmu.regs[rn] = v; } break; + case MMU_R_TLBX: + /* Bit 31 is read-only. */ + env->mmu.regs[rn] = deposit32(env->mmu.regs[rn], 0, 31, v); + break; case MMU_R_TLBSX: { struct microblaze_mmu_lookup lu;