mirror of https://github.com/xemu-project/xemu.git
hw/intc/arm_gicv3_its: Use FIELD macros for DTEs
Currently the ITS code that reads and writes DTEs uses open-coded shift-and-mask to assemble the various fields into the 64-bit DTE word. The names of the macros used for mask and shift values are also somewhat inconsistent, and don't follow our usual convention that a MASK macro should specify the bits in their place in the word. Replace all these with use of the FIELD macro. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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@ -114,7 +114,7 @@ static bool update_ite(GICv3ITSState *s, uint32_t eventid, uint64_t dte,
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uint64_t itt_addr;
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MemTxResult res = MEMTX_OK;
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itt_addr = (dte & GITS_DTE_ITTADDR_MASK) >> GITS_DTE_ITTADDR_SHIFT;
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itt_addr = FIELD_EX64(dte, DTE, ITTADDR);
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itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */
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address_space_stq_le(as, itt_addr + (eventid * (sizeof(uint64_t) +
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@ -141,7 +141,7 @@ static bool get_ite(GICv3ITSState *s, uint32_t eventid, uint64_t dte,
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bool status = false;
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IteEntry ite = {};
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itt_addr = (dte & GITS_DTE_ITTADDR_MASK) >> GITS_DTE_ITTADDR_SHIFT;
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itt_addr = FIELD_EX64(dte, DTE, ITTADDR);
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itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */
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ite.itel = address_space_ldq_le(as, itt_addr +
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@ -255,10 +255,10 @@ static bool process_its_cmd(GICv3ITSState *s, uint64_t value, uint32_t offset,
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if (res != MEMTX_OK) {
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return result;
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}
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dte_valid = dte & TABLE_ENTRY_VALID_MASK;
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dte_valid = FIELD_EX64(dte, DTE, VALID);
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if (dte_valid) {
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max_eventid = (1UL << (((dte >> 1U) & SIZE_MASK) + 1));
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max_eventid = 1UL << (FIELD_EX64(dte, DTE, SIZE) + 1);
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ite_valid = get_ite(s, eventid, dte, &icid, &pIntid, &res);
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@ -375,10 +375,8 @@ static bool process_mapti(GICv3ITSState *s, uint64_t value, uint32_t offset,
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if (res != MEMTX_OK) {
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return result;
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}
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dte_valid = dte & TABLE_ENTRY_VALID_MASK;
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max_eventid = (1UL << (((dte >> 1U) & SIZE_MASK) + 1));
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dte_valid = FIELD_EX64(dte, DTE, VALID);
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max_eventid = 1UL << (FIELD_EX64(dte, DTE, SIZE) + 1);
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max_Intid = (1ULL << (GICD_TYPER_IDBITS + 1)) - 1;
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if ((devid > s->dt.max_ids) || (icid > s->ct.max_ids)
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@ -529,9 +527,9 @@ static bool update_dte(GICv3ITSState *s, uint32_t devid, bool valid,
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if (s->dt.valid) {
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if (valid) {
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/* add mapping entry to device table */
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dte = (valid & TABLE_ENTRY_VALID_MASK) |
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((size & SIZE_MASK) << 1U) |
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(itt_addr << GITS_DTE_ITTADDR_SHIFT);
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dte = FIELD_DP64(dte, DTE, VALID, 1);
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dte = FIELD_DP64(dte, DTE, SIZE, size);
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dte = FIELD_DP64(dte, DTE, ITTADDR, itt_addr);
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}
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} else {
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return true;
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@ -393,9 +393,10 @@ FIELD(ITE_H, VPEID, 16, 16)
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* Valid = 1 bit,ITTAddr = 44 bits,Size = 5 bits
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*/
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#define GITS_DTE_SIZE (0x8ULL)
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#define GITS_DTE_ITTADDR_SHIFT 6
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#define GITS_DTE_ITTADDR_MASK MAKE_64BIT_MASK(GITS_DTE_ITTADDR_SHIFT, \
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ITTADDR_LENGTH)
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FIELD(DTE, VALID, 0, 1)
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FIELD(DTE, SIZE, 1, 5)
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FIELD(DTE, ITTADDR, 6, 44)
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/*
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* 8 bytes Collection Table Entry size
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