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hw/mips/boston: Massage memory map information 

Use memmap array to uinfy address of memory map.
That would allow us reuse address information for FDT generation.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[PMD: Use local 'regaddr' in gen_firmware(), fix coding style]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211002184539.169-2-jiaxun.yang@flygoat.com>
This commit is contained in:
Jiaxun Yang 2021-10-02 19:45:37 +01:00 committed by Philippe Mathieu-Daudé
parent 719f874b83
commit e07f3e265b
1 changed files with 80 additions and 28 deletions
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108
hw/mips/boston.c
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@ -64,6 +64,44 @@ struct BostonState {
hwaddr fdt_base; hwaddr fdt_base;
}; };
enum {
BOSTON_LOWDDR,
BOSTON_PCIE0,
BOSTON_PCIE1,
BOSTON_PCIE2,
BOSTON_PCIE2_MMIO,
BOSTON_CM,
BOSTON_GIC,
BOSTON_CDMM,
BOSTON_CPC,
BOSTON_PLATREG,
BOSTON_UART,
BOSTON_LCD,
BOSTON_FLASH,
BOSTON_PCIE1_MMIO,
BOSTON_PCIE0_MMIO,
BOSTON_HIGHDDR,
};
static const MemMapEntry boston_memmap[] = {
[BOSTON_LOWDDR] = { 0x0, 0x10000000 },
[BOSTON_PCIE0] = { 0x10000000, 0x2000000 },
[BOSTON_PCIE1] = { 0x12000000, 0x2000000 },
[BOSTON_PCIE2] = { 0x14000000, 0x2000000 },
[BOSTON_PCIE2_MMIO] = { 0x16000000, 0x100000 },
[BOSTON_CM] = { 0x16100000, 0x20000 },
[BOSTON_GIC] = { 0x16120000, 0x20000 },
[BOSTON_CDMM] = { 0x16140000, 0x8000 },
[BOSTON_CPC] = { 0x16200000, 0x8000 },
[BOSTON_PLATREG] = { 0x17ffd000, 0x1000 },
[BOSTON_UART] = { 0x17ffe000, 0x20 },
[BOSTON_LCD] = { 0x17fff000, 0x8 },
[BOSTON_FLASH] = { 0x18000000, 0x8000000 },
[BOSTON_PCIE1_MMIO] = { 0x20000000, 0x20000000 },
[BOSTON_PCIE0_MMIO] = { 0x40000000, 0x40000000 },
[BOSTON_HIGHDDR] = { 0x80000000, 0x0 },
};
enum boston_plat_reg { enum boston_plat_reg {
PLAT_FPGA_BUILD = 0x00, PLAT_FPGA_BUILD = 0x00,
PLAT_CORE_CL = 0x04, PLAT_CORE_CL = 0x04,
@ -275,24 +313,24 @@ type_init(boston_register_types)
static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr) static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr)
{ {
const uint32_t cm_base = 0x16100000; uint64_t regaddr;
const uint32_t gic_base = 0x16120000;
const uint32_t cpc_base = 0x16200000;
/* Move CM GCRs */ /* Move CM GCRs */
bl_gen_write_ulong(&p, regaddr = cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS),
cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS), bl_gen_write_ulong(&p, regaddr,
cm_base); boston_memmap[BOSTON_CM].base);
/* Move & enable GIC GCRs */ /* Move & enable GIC GCRs */
bl_gen_write_ulong(&p, regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base
cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE_OFS), + GCR_GIC_BASE_OFS),
gic_base | GCR_GIC_BASE_GICEN_MSK); bl_gen_write_ulong(&p, regaddr,
boston_memmap[BOSTON_GIC].base | GCR_GIC_BASE_GICEN_MSK);
/* Move & enable CPC GCRs */ /* Move & enable CPC GCRs */
bl_gen_write_ulong(&p, regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base
cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE_OFS), + GCR_CPC_BASE_OFS),
cpc_base | GCR_CPC_BASE_CPCEN_MSK); bl_gen_write_ulong(&p, regaddr,
boston_memmap[BOSTON_CPC].base | GCR_CPC_BASE_CPCEN_MSK);
/* /*
* Setup argument registers to follow the UHI boot protocol: * Setup argument registers to follow the UHI boot protocol:
@ -333,8 +371,9 @@ static const void *boston_fdt_filter(void *opaque, const void *fdt_orig,
ram_low_sz = MIN(256 * MiB, machine->ram_size); ram_low_sz = MIN(256 * MiB, machine->ram_size);
ram_high_sz = machine->ram_size - ram_low_sz; ram_high_sz = machine->ram_size - ram_low_sz;
qemu_fdt_setprop_sized_cells(fdt, "/memory@0", "reg", qemu_fdt_setprop_sized_cells(fdt, "/memory@0", "reg",
1, 0x00000000, 1, ram_low_sz, 1, boston_memmap[BOSTON_LOWDDR].base, 1, ram_low_sz,
1, 0x90000000, 1, ram_high_sz); 1, boston_memmap[BOSTON_HIGHDDR].base + ram_low_sz,
1, ram_high_sz);
fdt = g_realloc(fdt, fdt_totalsize(fdt)); fdt = g_realloc(fdt, fdt_totalsize(fdt));
qemu_fdt_dumpdtb(fdt, fdt_sz); qemu_fdt_dumpdtb(fdt, fdt_sz);
@ -438,11 +477,15 @@ static void boston_mach_init(MachineState *machine)
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
flash = g_new(MemoryRegion, 1); flash = g_new(MemoryRegion, 1);
memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB, memory_region_init_rom(flash, NULL, "boston.flash",
&error_fatal); boston_memmap[BOSTON_FLASH].size, &error_fatal);
memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0); memory_region_add_subregion_overlap(sys_mem,
boston_memmap[BOSTON_FLASH].base,
flash, 0);
memory_region_add_subregion_overlap(sys_mem, 0x80000000, machine->ram, 0); memory_region_add_subregion_overlap(sys_mem,
boston_memmap[BOSTON_HIGHDDR].base,
machine->ram, 0);
ddr_low_alias = g_new(MemoryRegion, 1); ddr_low_alias = g_new(MemoryRegion, 1);
memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr", memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr",
@ -451,32 +494,41 @@ static void boston_mach_init(MachineState *machine)
memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0); memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0);
xilinx_pcie_init(sys_mem, 0, xilinx_pcie_init(sys_mem, 0,
0x10000000, 32 * MiB, boston_memmap[BOSTON_PCIE0].base,
0x40000000, 1 * GiB, boston_memmap[BOSTON_PCIE0].size,
boston_memmap[BOSTON_PCIE0_MMIO].base,
boston_memmap[BOSTON_PCIE0_MMIO].size,
get_cps_irq(&s->cps, 2), false); get_cps_irq(&s->cps, 2), false);
xilinx_pcie_init(sys_mem, 1, xilinx_pcie_init(sys_mem, 1,
0x12000000, 32 * MiB, boston_memmap[BOSTON_PCIE1].base,
0x20000000, 512 * MiB, boston_memmap[BOSTON_PCIE1].size,
boston_memmap[BOSTON_PCIE1_MMIO].base,
boston_memmap[BOSTON_PCIE1_MMIO].size,
get_cps_irq(&s->cps, 1), false); get_cps_irq(&s->cps, 1), false);
pcie2 = xilinx_pcie_init(sys_mem, 2, pcie2 = xilinx_pcie_init(sys_mem, 2,
0x14000000, 32 * MiB, boston_memmap[BOSTON_PCIE2].base,
0x16000000, 1 * MiB, boston_memmap[BOSTON_PCIE2].size,
boston_memmap[BOSTON_PCIE2_MMIO].base,
boston_memmap[BOSTON_PCIE2_MMIO].size,
get_cps_irq(&s->cps, 0), true); get_cps_irq(&s->cps, 0), true);
platreg = g_new(MemoryRegion, 1); platreg = g_new(MemoryRegion, 1);
memory_region_init_io(platreg, NULL, &boston_platreg_ops, s, memory_region_init_io(platreg, NULL, &boston_platreg_ops, s,
"boston-platregs", 0x1000); "boston-platregs",
memory_region_add_subregion_overlap(sys_mem, 0x17ffd000, platreg, 0); boston_memmap[BOSTON_PLATREG].size);
memory_region_add_subregion_overlap(sys_mem,
boston_memmap[BOSTON_PLATREG].base, platreg, 0);
s->uart = serial_mm_init(sys_mem, 0x17ffe000, 2, s->uart = serial_mm_init(sys_mem, boston_memmap[BOSTON_UART].base, 2,
get_cps_irq(&s->cps, 3), 10000000, get_cps_irq(&s->cps, 3), 10000000,
serial_hd(0), DEVICE_NATIVE_ENDIAN); serial_hd(0), DEVICE_NATIVE_ENDIAN);
lcd = g_new(MemoryRegion, 1); lcd = g_new(MemoryRegion, 1);
memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8); memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8);
memory_region_add_subregion_overlap(sys_mem, 0x17fff000, lcd, 0); memory_region_add_subregion_overlap(sys_mem,
boston_memmap[BOSTON_LCD].base, lcd, 0);
chr = qemu_chr_new("lcd", "vc:320x240", NULL); chr = qemu_chr_new("lcd", "vc:320x240", NULL);
qemu_chr_fe_init(&s->lcd_display, chr, NULL); qemu_chr_fe_init(&s->lcd_display, chr, NULL);