mirror of https://github.com/xemu-project/xemu.git
hw/mips/boston: Massage memory map information
Use memmap array to uinfy address of memory map. That would allow us reuse address information for FDT generation. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: Use local 'regaddr' in gen_firmware(), fix coding style] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211002184539.169-2-jiaxun.yang@flygoat.com>
This commit is contained in:
Jiaxun Yang
Philippe Mathieu-Daudé
parent
719f874b83
commit
e07f3e265b
108
hw/mips/boston.c
108
hw/mips/boston.c
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@ -64,6 +64,44 @@ struct BostonState {
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hwaddr fdt_base;
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};
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enum {
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BOSTON_LOWDDR,
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BOSTON_PCIE0,
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BOSTON_PCIE1,
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BOSTON_PCIE2,
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BOSTON_PCIE2_MMIO,
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BOSTON_CM,
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BOSTON_GIC,
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BOSTON_CDMM,
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BOSTON_CPC,
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BOSTON_PLATREG,
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BOSTON_UART,
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BOSTON_LCD,
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BOSTON_FLASH,
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BOSTON_PCIE1_MMIO,
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BOSTON_PCIE0_MMIO,
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BOSTON_HIGHDDR,
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};
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static const MemMapEntry boston_memmap[] = {
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[BOSTON_LOWDDR] = { 0x0, 0x10000000 },
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[BOSTON_PCIE0] = { 0x10000000, 0x2000000 },
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[BOSTON_PCIE1] = { 0x12000000, 0x2000000 },
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[BOSTON_PCIE2] = { 0x14000000, 0x2000000 },
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[BOSTON_PCIE2_MMIO] = { 0x16000000, 0x100000 },
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[BOSTON_CM] = { 0x16100000, 0x20000 },
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[BOSTON_GIC] = { 0x16120000, 0x20000 },
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[BOSTON_CDMM] = { 0x16140000, 0x8000 },
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[BOSTON_CPC] = { 0x16200000, 0x8000 },
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[BOSTON_PLATREG] = { 0x17ffd000, 0x1000 },
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[BOSTON_UART] = { 0x17ffe000, 0x20 },
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[BOSTON_LCD] = { 0x17fff000, 0x8 },
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[BOSTON_FLASH] = { 0x18000000, 0x8000000 },
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[BOSTON_PCIE1_MMIO] = { 0x20000000, 0x20000000 },
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[BOSTON_PCIE0_MMIO] = { 0x40000000, 0x40000000 },
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[BOSTON_HIGHDDR] = { 0x80000000, 0x0 },
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};
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enum boston_plat_reg {
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PLAT_FPGA_BUILD = 0x00,
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PLAT_CORE_CL = 0x04,
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@ -275,24 +313,24 @@ type_init(boston_register_types)
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static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr)
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{
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const uint32_t cm_base = 0x16100000;
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const uint32_t gic_base = 0x16120000;
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const uint32_t cpc_base = 0x16200000;
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uint64_t regaddr;
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/* Move CM GCRs */
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bl_gen_write_ulong(&p,
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cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS),
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cm_base);
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regaddr = cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS),
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bl_gen_write_ulong(&p, regaddr,
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boston_memmap[BOSTON_CM].base);
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/* Move & enable GIC GCRs */
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bl_gen_write_ulong(&p,
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cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE_OFS),
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gic_base | GCR_GIC_BASE_GICEN_MSK);
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regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base
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+ GCR_GIC_BASE_OFS),
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bl_gen_write_ulong(&p, regaddr,
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boston_memmap[BOSTON_GIC].base | GCR_GIC_BASE_GICEN_MSK);
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/* Move & enable CPC GCRs */
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bl_gen_write_ulong(&p,
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cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE_OFS),
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cpc_base | GCR_CPC_BASE_CPCEN_MSK);
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regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base
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+ GCR_CPC_BASE_OFS),
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bl_gen_write_ulong(&p, regaddr,
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boston_memmap[BOSTON_CPC].base | GCR_CPC_BASE_CPCEN_MSK);
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/*
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* Setup argument registers to follow the UHI boot protocol:
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@ -333,8 +371,9 @@ static const void *boston_fdt_filter(void *opaque, const void *fdt_orig,
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ram_low_sz = MIN(256 * MiB, machine->ram_size);
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ram_high_sz = machine->ram_size - ram_low_sz;
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qemu_fdt_setprop_sized_cells(fdt, "/memory@0", "reg",
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1, 0x00000000, 1, ram_low_sz,
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1, 0x90000000, 1, ram_high_sz);
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1, boston_memmap[BOSTON_LOWDDR].base, 1, ram_low_sz,
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1, boston_memmap[BOSTON_HIGHDDR].base + ram_low_sz,
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1, ram_high_sz);
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fdt = g_realloc(fdt, fdt_totalsize(fdt));
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qemu_fdt_dumpdtb(fdt, fdt_sz);
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@ -438,11 +477,15 @@ static void boston_mach_init(MachineState *machine)
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sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
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flash = g_new(MemoryRegion, 1);
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memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB,
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&error_fatal);
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memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0);
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memory_region_init_rom(flash, NULL, "boston.flash",
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boston_memmap[BOSTON_FLASH].size, &error_fatal);
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memory_region_add_subregion_overlap(sys_mem,
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boston_memmap[BOSTON_FLASH].base,
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flash, 0);
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memory_region_add_subregion_overlap(sys_mem, 0x80000000, machine->ram, 0);
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memory_region_add_subregion_overlap(sys_mem,
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boston_memmap[BOSTON_HIGHDDR].base,
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machine->ram, 0);
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ddr_low_alias = g_new(MemoryRegion, 1);
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memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr",
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@ -451,32 +494,41 @@ static void boston_mach_init(MachineState *machine)
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memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0);
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xilinx_pcie_init(sys_mem, 0,
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0x10000000, 32 * MiB,
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0x40000000, 1 * GiB,
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boston_memmap[BOSTON_PCIE0].base,
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boston_memmap[BOSTON_PCIE0].size,
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boston_memmap[BOSTON_PCIE0_MMIO].base,
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boston_memmap[BOSTON_PCIE0_MMIO].size,
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get_cps_irq(&s->cps, 2), false);
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xilinx_pcie_init(sys_mem, 1,
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0x12000000, 32 * MiB,
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0x20000000, 512 * MiB,
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boston_memmap[BOSTON_PCIE1].base,
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boston_memmap[BOSTON_PCIE1].size,
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boston_memmap[BOSTON_PCIE1_MMIO].base,
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boston_memmap[BOSTON_PCIE1_MMIO].size,
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get_cps_irq(&s->cps, 1), false);
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pcie2 = xilinx_pcie_init(sys_mem, 2,
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0x14000000, 32 * MiB,
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0x16000000, 1 * MiB,
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boston_memmap[BOSTON_PCIE2].base,
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boston_memmap[BOSTON_PCIE2].size,
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boston_memmap[BOSTON_PCIE2_MMIO].base,
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boston_memmap[BOSTON_PCIE2_MMIO].size,
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get_cps_irq(&s->cps, 0), true);
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platreg = g_new(MemoryRegion, 1);
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memory_region_init_io(platreg, NULL, &boston_platreg_ops, s,
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"boston-platregs", 0x1000);
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memory_region_add_subregion_overlap(sys_mem, 0x17ffd000, platreg, 0);
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"boston-platregs",
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boston_memmap[BOSTON_PLATREG].size);
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memory_region_add_subregion_overlap(sys_mem,
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boston_memmap[BOSTON_PLATREG].base, platreg, 0);
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s->uart = serial_mm_init(sys_mem, 0x17ffe000, 2,
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s->uart = serial_mm_init(sys_mem, boston_memmap[BOSTON_UART].base, 2,
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get_cps_irq(&s->cps, 3), 10000000,
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serial_hd(0), DEVICE_NATIVE_ENDIAN);
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lcd = g_new(MemoryRegion, 1);
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memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8);
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memory_region_add_subregion_overlap(sys_mem, 0x17fff000, lcd, 0);
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memory_region_add_subregion_overlap(sys_mem,
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boston_memmap[BOSTON_LCD].base, lcd, 0);
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chr = qemu_chr_new("lcd", "vc:320x240", NULL);
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qemu_chr_fe_init(&s->lcd_display, chr, NULL);
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