From dfae46c3ba4880036a3df0b0aafca0c792b7cb9d Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 3 Apr 2023 19:28:36 +0200 Subject: [PATCH] target/mips: tcg: detect out-of-bounds accesses to cpu_gpr and cpu_gpr_hi In some cases (for example gen_compute_branch_nm in nanomips_translate.c.inc) registers can be unused on some paths and a negative value is passed in that case: gen_compute_branch_nm(ctx, OPC_BPOSGE32, 4, -1, -2, imm << 1); To avoid an out of bounds access in those cases, introduce assertions. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- target/mips/tcg/translate.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 1fb4ef7127..999fbb7cc1 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1223,6 +1223,7 @@ static const char regnames_LO[][4] = { /* General purpose registers moves. */ void gen_load_gpr(TCGv t, int reg) { + assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr)); if (reg == 0) { tcg_gen_movi_tl(t, 0); } else { @@ -1232,6 +1233,7 @@ void gen_load_gpr(TCGv t, int reg) void gen_store_gpr(TCGv t, int reg) { + assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr)); if (reg != 0) { tcg_gen_mov_tl(cpu_gpr[reg], t); } @@ -1240,6 +1242,7 @@ void gen_store_gpr(TCGv t, int reg) #if defined(TARGET_MIPS64) void gen_load_gpr_hi(TCGv_i64 t, int reg) { + assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr_hi)); if (reg == 0) { tcg_gen_movi_i64(t, 0); } else { @@ -1249,6 +1252,7 @@ void gen_load_gpr_hi(TCGv_i64 t, int reg) void gen_store_gpr_hi(TCGv_i64 t, int reg) { + assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr_hi)); if (reg != 0) { tcg_gen_mov_i64(cpu_gpr_hi[reg], t); }