From dcc3a21209a8eeae0fe43966012f8e08d3566f98 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 14 Jul 2017 09:54:59 -1000 Subject: [PATCH] target/arm: [a64] Move page and ss checks to init_disas_context Since AArch64 uses a fixed-width ISA, we can pre-compute the number of insns remaining on the page. Also, we can check for single-step once. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 25c6622825..9017e30510 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11206,6 +11206,7 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase, DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; ARMCPU *arm_cpu = arm_env_get_cpu(env); + int bound; dc->pc = dc->base.pc_first; dc->condjmp = 0; @@ -11254,8 +11255,14 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->is_ldex = false; dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el); - dc->next_page_start = - (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; + /* Bound the number of insns to execute to those left on the page. */ + bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; + + /* If architectural single step active, limit to 1. */ + if (dc->ss_active) { + bound = 1; + } + max_insns = MIN(max_insns, bound); init_tmp_a64_array(dc); @@ -11323,12 +11330,6 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) disas_a64_insn(env, dc); } - if (dc->base.is_jmp == DISAS_NEXT) { - if (dc->ss_active || dc->pc >= dc->next_page_start) { - dc->base.is_jmp = DISAS_TOO_MANY; - } - } - dc->base.pc_next = dc->pc; translator_loop_temp_check(&dc->base); }