mirror of https://github.com/xemu-project/xemu.git
hw/loongarch: Add some devices support for 3A5000.
1.Add uart,virtio-net,vga and usb for 3A5000. 2.Add irq set and map for the pci host. Non pci device use irq 0-16, pci device use 16-64. 3.Add some unimplented device to emulate guest unused memory space. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-38-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Xiaojuan Yang
Richard Henderson
parent
256309e188
commit
dc93b8df8a
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@ -2,6 +2,13 @@ config LOONGARCH_VIRT
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bool
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select PCI
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select PCI_EXPRESS_GENERIC_BRIDGE
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imply VGA_PCI
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imply VIRTIO_VGA
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imply PCI_DEVICES
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select ISA_BUS
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select SERIAL
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select SERIAL_ISA
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select VIRTIO_PCI
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select LOONGARCH_IPI
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select LOONGARCH_PCH_PIC
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select LOONGARCH_PCH_MSI
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@ -9,6 +9,7 @@
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#include "qemu/datadir.h"
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#include "qapi/error.h"
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#include "hw/boards.h"
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#include "hw/char/serial.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/qtest.h"
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#include "sysemu/runstate.h"
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@ -16,14 +17,88 @@
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#include "sysemu/rtc.h"
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#include "hw/loongarch/virt.h"
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#include "exec/address-spaces.h"
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#include "hw/irq.h"
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#include "net/net.h"
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#include "hw/intc/loongarch_ipi.h"
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#include "hw/intc/loongarch_extioi.h"
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#include "hw/intc/loongarch_pch_pic.h"
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#include "hw/intc/loongarch_pch_msi.h"
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#include "hw/pci-host/ls7a.h"
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#include "hw/pci-host/gpex.h"
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#include "hw/misc/unimp.h"
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#include "target/loongarch/cpu.h"
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static void loongarch_devices_init(DeviceState *pch_pic)
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{
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DeviceState *gpex_dev;
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SysBusDevice *d;
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PCIBus *pci_bus;
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MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg;
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MemoryRegion *mmio_alias, *mmio_reg;
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int i;
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gpex_dev = qdev_new(TYPE_GPEX_HOST);
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d = SYS_BUS_DEVICE(gpex_dev);
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sysbus_realize_and_unref(d, &error_fatal);
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pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus;
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/* Map only part size_ecam bytes of ECAM space */
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ecam_alias = g_new0(MemoryRegion, 1);
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ecam_reg = sysbus_mmio_get_region(d, 0);
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memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam",
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ecam_reg, 0, LS_PCIECFG_SIZE);
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memory_region_add_subregion(get_system_memory(), LS_PCIECFG_BASE,
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ecam_alias);
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/* Map PCI mem space */
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mmio_alias = g_new0(MemoryRegion, 1);
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mmio_reg = sysbus_mmio_get_region(d, 1);
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memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio",
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mmio_reg, LS7A_PCI_MEM_BASE, LS7A_PCI_MEM_SIZE);
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memory_region_add_subregion(get_system_memory(), LS7A_PCI_MEM_BASE,
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mmio_alias);
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/* Map PCI IO port space. */
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pio_alias = g_new0(MemoryRegion, 1);
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pio_reg = sysbus_mmio_get_region(d, 2);
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memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg,
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LS7A_PCI_IO_OFFSET, LS7A_PCI_IO_SIZE);
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memory_region_add_subregion(get_system_memory(), LS7A_PCI_IO_BASE,
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pio_alias);
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for (i = 0; i < GPEX_NUM_IRQS; i++) {
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sysbus_connect_irq(d, i,
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qdev_get_gpio_in(pch_pic, 16 + i));
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gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i);
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}
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serial_mm_init(get_system_memory(), LS7A_UART_BASE, 0,
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qdev_get_gpio_in(pch_pic,
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LS7A_UART_IRQ - PCH_PIC_IRQ_OFFSET),
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115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
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/* Network init */
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for (i = 0; i < nb_nics; i++) {
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NICInfo *nd = &nd_table[i];
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if (!nd->model) {
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nd->model = g_strdup("virtio");
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}
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pci_nic_init_nofail(nd, pci_bus, nd->model, NULL);
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}
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/* VGA setup */
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pci_vga_init(pci_bus);
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/*
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* There are some invalid guest memory access.
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* Create some unimplemented devices to emulate this.
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*/
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create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4);
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}
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static void loongarch_irq_init(LoongArchMachineState *lams)
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{
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MachineState *ms = MACHINE(lams);
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@ -118,6 +193,8 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
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qdev_connect_gpio_out(DEVICE(d), i,
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qdev_get_gpio_in(extioi, i + PCH_MSI_IRQ_START));
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}
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loongarch_devices_init(pch_pic);
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}
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static void loongarch_init(MachineState *machine)
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@ -17,6 +17,11 @@
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#define LS7A_PCI_MEM_BASE 0x40000000UL
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#define LS7A_PCI_MEM_SIZE 0x40000000UL
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#define LS7A_PCI_IO_OFFSET 0x4000
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#define LS_PCIECFG_BASE 0x20000000
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#define LS_PCIECFG_SIZE 0x08000000
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#define LS7A_PCI_IO_BASE 0x18004000UL
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#define LS7A_PCI_IO_SIZE 0xC000
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#define LS7A_PCH_REG_BASE 0x10000000UL
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#define LS7A_IOAPIC_REG_BASE (LS7A_PCH_REG_BASE)
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@ -30,4 +35,6 @@
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#define PCH_PIC_IRQ_OFFSET 64
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#define LS7A_DEVICE_IRQS 16
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#define LS7A_PCI_IRQS 48
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#define LS7A_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2)
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#define LS7A_UART_BASE 0x1fe001e0
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#endif
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